KSZ8993 Micrel Inc, KSZ8993 Datasheet
KSZ8993
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KSZ8993 Summary of contents
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KS8993 General Description The KS8993 contains three 10/100 physical layer transceiv- ers, three MAC (Media Access Control) units with an inte- grated layer 2 switch. The device runs in two modes. The first mode is a three port integrated switch ...
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... Commercial temperature range +70 C • Industrial temperature range: – +85 C • Available in 128-pin PQFP with single 2.5V power supply KS8993 Ordering Information Part Number Temperature Range Standard Pb-Free KS8993 KSZ8993 +70 C KS8993I – – + Micrel Package 128-Pin PQFP 128-Pin PQFP May 2005 ...
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KS8993 Revision History Revision Date Summary of Changes 1.00 04/13/00 Document origination 1.01 05/31/00 Miscellaneous changes 1.02 06/08/00 Index repair 1.03 09/20/00 MII forward correction. MRXD[3:1] correction. 1.04 10/30/00 Update voltage ratings. 1.05 10/31/00 Correct I/O descriptions. 1.06 11/08/00 Correct ...
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KS8993 Table of Contents System Level Applications .............................................................................................................................................................. 5 Pin Description .............................................................................................................................................................................. 6 I/O Grouping .............................................................................................................................................................................. 9 I/O Descriptions ............................................................................................................................................................................ 10 Pin Configuration ........................................................................................................................................................................... 15 Functional Overview: Physical Layer Transceiver ..................................................................................................................... 16 100BaseTX Transmit ............................................................................................................................................................... 16 100BaseTX Receive ................................................................................................................................................................ 16 ...
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KS8993 System Level Applications The KS8993 can be configured to fit either in a three port 10/ 100 application two port 10/100 network interface with an extra MII or SNI port. This MII/SNI port can be connected ...
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KS8993 Pin Description Pin Number Pin Name Type 1 GND_ANA GND 2 MUX[2] 3 MUX[1] 4 GND_RX[1] GND 5 RXP[1] 6 RXM[1] 7 VDD_RX[1] 8 VREF[1] 9 TXP[1] 10 TXM[1] 11 GND_TX[1] GND 12 VDD_TX[1] 13 VDD_BG 14 ISET 15 ...
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KS8993 Pin Number Pin Name Type 39 TEST[1] 40 TEST[2] 41 GND_RCV[2] GND 42 VDD_RCV[2] 43 GND_RCV[3] GND 44 VDD_RCV[3] 45 VMDIS 46 FFLOW2# 47 PV32 48 PV31 49 PV23 50 FFLOW1# 51 PV21 52 PV13 53 PV12 54 DISAN3 ...
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KS8993 Pin Number Pin Name Type 77 MODESEL[3] 78 MODESEL[2] 79 MODESEL[1] 80 MODESEL[0] 81 TESTEN 82 SCANEN 83 RST# 84 VDD 85 GND GND 86 LED[1][3] 87 LED[1][2] 88 LED[1][1] 89 LED[1][0] 90 LED[2][3] 91 LED[2][2] 92 LED[2][1] 93 ...
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KS8993 Pin Number Pin Name Type 116 P1_PP 117 P1_TAGINS 118 P2_TAGINS 119 P3_TAGINS 120 P3_TAGRM 121 P2_TAGRM 122 P1_TAGRM 123 VDD_RCV[1] 124 GND_RCV[1] GND 125 X2 126 X1 127 FXSD[1] 128 AOUT Note 1. Pwr = power supply GND ...
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KS8993 I/O Descriptions Group I/O Names Active Status PHY RXP[1:3] Analog RXM[1:3] TXP[1:3] Analog TXM[1:3] FXSD[1:3] H VREF[1:3] Analog ISET Analog MII MRXD[0:3] H MRXDV H MCRS H MCOL H MCOLIN H MRXCLK Clock MTXD[0:3] H MTXEN H MTXER H ...
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KS8993 Group I/O Names Active Status LED[1:3][ MODESEL[3:0] H FFLOW1# L FFLOW2# L LED[1][3] LED[1][2] LED[1][1] May 2005 Description Output (after reset). Mode 0: Link + Activity (toggle = receiving or transmitting, constant low = link, constant high ...
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KS8993 Group I/O Names Active Status LED[1][0] LED[2][3] LED[2][2] LED[2][1] LED[2][0] LED[3][3] LED[3][2:0] MRXD[3:1] MRXD0 MCOL DISAN3 MIIS[1:0] H KS8993 Description Programs buffer allocation per port at reset time. Use the following table to select the option. Pulled low = ...
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KS8993 Group I/O Names Active Status VMDIS H PRSV H PBASE[2:0] H PV12 H PV13 PV21 PV23 PV31 PV32 P[3:1]_1PEN H P[3:1]_PP H P[3:1]_TAGINS H P[3:1]_TAGRM H P[3:1]_TXQ2 H May 2005 Description VLAN Mismatch Discard control. Pulled low = Constrict ...
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KS8993 Group I/O Names Active Status PRSEL[1:0] H CTRL X1 Clock X2 Clock RST# L TEST TESTEN H SCANEN H AOUT H MUX[1:2] H TEST[1:2] H PWR VDD_RX[1:3] GND_RX[1:3] VDD_TX[1:3] GND_TX[1:3] VDD_RCV[1:3] GND_RCV[1:3] VDD_PLL GND_PLL GND_ANA GND_BG VDD_BG VDD VDD_IO ...
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KS8993 Pin Configuration 103 PBASE2 PBASE1 PBASE0 P3_1PEN P2_1PEN P1_1PEN P3_TXQ2 P2_TXQ2 P1_TXQ2 GND VDD P3_PP P2_PP P1_PP P1_TAGINS P2_TAGINS P3_TAGINS P3_TAGRM P2_TAGRM P1_TAGRM VDD_RCV[1] GND_RCV[ FXSD[1] AOUT 1 May 2005 128-Pin PQFP (PQ) 15 Micrel 65 MRXDV ...
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KS8993 Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the ...
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KS8993 squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL ...
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KS8993 Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8993 is guaranteed to learn 1K addresses and distinguishes itself ...
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KS8993 Back off Algorithm The KS8993 implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional “aggressive mode” back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration. Late Collision If a transmit ...
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KS8993 P1_V : (1,0,1) P2_V : (1,1,0) P3_V : (1,1,1) In the above setting, there are two VLANs. VLAN 1 includes ports 1,3 and VLAN 2 includes ports 2, 3. Port 3 belongs to both VLANs. If vmdis = 1, ...
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KS8993 MII Interface Operation The MII (Media Independent Interface) operates in either a forward or reverse mode. In the forward mode, the KS8993 MII acts like a MAC and in the reverse mode, it acts like a PHY device. This ...
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KS8993 SNI Interface (7-wire) Operation The SNI (Serial Network Interface) is intended to interface with some controllers used for network layer protocol processing. KS8993 acts like a PHY device to external controllers. This interface can be directly connected to these ...
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KS8993 Absolute Maximum Ratings Supply Voltage ( DD_RX DD_TX DD_BG DD_PLL ........................................ –0.5V to +3.0V DD_RCV ................................................... –0.5V to +4.0V DD_IO Input Voltage (All Inputs) ............................. –0.5V ...
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KS8993 Timing Diagrams Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Symbol Parameter t Clock Cycle CYC t Output Valid OV KS8993 Figure 3. SNI (7-Wire) Input Timing Table 4. SNI (7-Wire) Input Timing ...
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KS8993 Figure 5. Reverse MII Timing–Receive Data from MII Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Table 6. Reverse MII Timing–Receive Data from MII Parameters May 2005 (100BaseT) (10BaseT) 25 Micrel Min Typ ...
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KS8993 Figure 6. Reverse MII Timing–Transmit Data to MII Symbol Parameter t Clock Cycle CYC t Output Valid OV Table 7. Reverse MII Timing–Transmit Data to MII Parameters KS8993 (100BaseT) (10BaseT) 26 Micrel Min Typ Max Units 40 ns 400 ...
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KS8993 Figure 7. Forward MII Timing–Receive Data from MII Symbol Parameter t Clock Cycle CYC t Set-Up Time S t Hold Time H Table 8. Forward MII Timing–Receive Data from MII Parameters May 2005 (100BaseT) (10BaseT) 27 Micrel Min Typ ...
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KS8993 Figure 8. Forward MII Timing–Transmit Data to MII Symbol Parameter t Clock Cycle CYC t Output Valid OV Table 9. Forward MII Timing–Transmit Data to MII KS8993 (100BaseT) (10BaseT) 28 Micrel Min Typ Max Units 40 ns 400 ns ...
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KS8993 Reference Circuit “I/O Description” See section for pull-up/pull-down and float information. Reset Circuit Diagram Micrel recommendeds the following discrete reset circuit as shown in Figure 9 when powering up the KS8993 device. For the application where the reset circuit ...
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KS8993 Figure 10. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up ...
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KS8993 4B/5B Coding In 100BaseTX and 100BaseFX the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4B/5B code. The extra code space is required to encode extra control (frame delineation) points. It ...
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KS8993 MLT3 Coding For 100BaseTX operation the NRZI (Non-Return to Zero Invert on ones) signal is line coded as MLT3. The net result of using MLT3 is to reduce the EMI (Electro Magnetic Interference) of the signal over twisted pair ...
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KS8993 802.1q VLAN and 802.1p Priority Frame The 3-bit of 802.1p priority is embedded into the 802.1q VLAN frame as described below: (bit) May 2005 802.1P Priority Figure 12. 802.1p and 802.1q Frame Format 33 802.1Q VLAN Micrel KS8993 ...
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KS8993 Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...
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KS8993 Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel ...