DS34S102GN+ Maxim Integrated Products, DS34S102GN+ Datasheet - Page 7

• Manufacturer Part Number: DS34S102GN+
• Description: IC TRANSPORT TDM DUAL 256-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS34S102GN+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5 Features
Global Features
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Clock Synthesizers
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TDM-over-Packet Block
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Rev: 032609
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
TDMoP Interfaces
Ethernet Interface
End-to-end TDM synchronization through the IP/MPLS domain by on-chip, per-port TDM clock recovery
64 independent bundles/connections, each with its own:
Packet loss compensation and handling of misordered packets
Glueless SDRAM interface
Complies with MPLS-Frame Relay Alliance Implementation Agreements 4.1, 5.1 and 8.0
Complies with ITU-T standards Y.1413 and Y.1414.
Complies with Metro Ethernet Forum 3 and 8
Complies with IETF RFC 4553 (SAToP), RFC 5086 (CESoPSN) and RFC 5087 (TDMoIP)
IEEE 1146.1 JTAG boundary scan
1.8V and 3.3V Operation with 5.0V tolerant I/O
Clocks to operate the TDMoP clock recovery machines can synthesized from a single clock input (10MHz,
19.44MHz, 38.88MHz or 77.76MHz on the CLK_HIGH pin)
Clock to operate TDMoP logic and SDRAM interface (50MHz or 75MHz) can be synthesized from a single
25MHz clock on the CLK_SYS pin
Enables transport of TDM services (E1, T1, E3, T3, STS-1) or serial data over packet-switched networks
SAToP payload-type machine maps/demaps unframed E1/T1/E3/T3/STS-1 or serial data flows to/from IP,
MPLS or Ethernet packets according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553.
CESoPSN payload-type machine maps/demaps structured E1/T1 data flows to/from IP, MPLS or Ethernet
packets with static assignment of timeslots inside a bundle according to ITU-T Y.1413, Y.1453, MEF 8, MFA
8.0.0 and IETF RFC 5086.
AAL1 payload-type machine maps/demaps E1/T1/E3/T3/STS-1 or serial data flows to/from IP, MPLS or
Ethernet packets according to ITU-T Y.1413, MEF 8, MFA 4.1 and IETF RFC 5087. For E1/T1 it supports
structured mode with/without CAS using 8-bit timeslot resolution, while implementing static timeslot allocation.
For E1/T1, E3/T3/STS-1 or serial interface it supports unstructured mode.
HDLC payload-type machine maps/demaps HDLC-based E1/T1/serial flow to/from IP, MPLS or Ethernet
packets. It supports 2-, 7- and 8-bit timeslot resolution (i.e. 16, 56, and 64 kbps respectively), as well as N x 64
kbps bundles. This is useful in applications where HDLC-based signaling interpretation is required (such as
ISDN D channel signaling termination, V.51/2, or GR-303), or for trunking packet-based applications (such as
Frame Relay), according to IETF RFC 4618.
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DS34S101: 1 E1/T1/serial TDM interface
DS34S102: 2 E1/T1/serial TDM interfaces
DS34S104: 4 E1/T1/serial TDM interfaces
DS34S108: 8 E1/T1/serial TDM interfaces
All four devices: optionally 1 high-speed E3/DS3/STS-1 TDM interface
All four devices: each interface optionally configurable for serial operation for V.35 and RS530
One 10/100 Mbps port configurable for MII, RMII or SSMII interface format
Half or full duplex operation
VLAN support according to 802.1p and 802.1Q including stacked tags
Fully compatible with IEEE 802.3 standard
Transmit and receive queues
Configurable jitter-buffer depth
Connection-level redundancy, with traffic duplication option
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