IDT89HPES3T3ZBNQG8 IDT, Integrated Device Technology Inc, IDT89HPES3T3ZBNQG8 Datasheet - Page 2

• Manufacturer Part Number: IDT89HPES3T3ZBNQG8
• Description: IC PCI SW 3LANE 3PORT 132-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES3T3ZBNQG8

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES3T3ZBNQG8

Product Description
latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully
compliant with PCI Express Base specification 1.1.
tion layers in compliance with PCI Express Base specification Revision 1.1. The PES3T3 can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity.
SMBus Interface
ridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O
expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin.
Hot-Plug Interface
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-
ever the state of a Hot-Plug output needs to be modified, the PES3T3 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES3T3. In response to an I/O expander interrupt, the PES3T3 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
IDT 89HPES3T3 Data Sheet
Utilizing standard PCI Express interconnect, the PES3T3 provides the most efficient fan-out solution for applications requiring x1 connectivity, low
The PES3T3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-
The PES3T3 contains an SMBus master interface. This master interface allows the default configuration register values of the PES3T3 to be over-
The PES3T3 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES3T3 utilizes
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Five General Purpose Input/Output Pins
Option A Package: 13mm x 13mm 144-ball BGA with 1mm ball spacing
Option B Package: 10mm x 10mm 132-ball QFN with 1mm ball spacing
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Four pins have selectable alternate functions
Figure 2 I/O Expansion Application
Processor
x1
LOM
GE
2 of 31
Bridge
PES3T3
North
Bridge
South
Processor
x1
1394
x1
Memory
Memory
Memory
Memory
October 8, 2010