IDT89HPES3T3ZBBCG IDT, Integrated Device Technology Inc, IDT89HPES3T3ZBBCG Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES3T3ZBBCG
• Description: IC PCI SW 3LANE 3PORT 144-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES3T3ZBBCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES3T3ZBBCG

IDT 89HPES3T3 Data Sheet
APWRDISN
Signal
Signal
CCLKDS
CCLKUS
PERSTN
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[7]
GPIO[9]
Type
Type
I/O
I/O
I/O
I/O
I/O
I
I
I
I
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
Auxiliary Power Disable Input. When this pin is active, it disables the
device from using auxiliary power supply.
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be override by modifying the SCLK bit in the downstream
port’s PCIELSTS register.
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.
Fundamental Reset. Assertion of this signal resets all logic inside the
PES3T3 and initiates a PCI Express fundamental reset.
Table 3 General Purpose I/O Pins
Table 4 System Pins (Part 1 of 2)
4 of 31
Name/Description
Name/Description
October 8, 2010