IDT89HPES4T4ZBBC IDT, Integrated Device Technology Inc, IDT89HPES4T4ZBBC Datasheet - Page 8

• Manufacturer Part Number: IDT89HPES4T4ZBBC
• Description: IC PCI SW 4LANE 4PORT 144-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES4T4ZBBC

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES4T4ZBBC

System Clock Parameters
AC Timing Characteristics
IDT 89HPES4T4 Data Sheet
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13.
PEREFCLK
Refclk
Refclk
T
V
T
1.
2.
3.
PCIe Transmit
UI
T
T
MAX-JITTER
T
T
T
IDLE
T
DATA
T
T
PCIe Receive
UI
T
R
jitter
SW
Parameter
TX-EYE
TX-EYE-MEDIAN-to-
TX-RISE,
TX- IDLE-MIN
TX-IDLE-SET-TO-
TX-IDLE-TO-DIFF-
TX-SKEW
BTEn
RX-EYE (with jitter)
, T
ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
AC coupling required.
Parameter
F
FREQ
DC
1
T
TX-FALL
Input reference clock frequency range
Duty cycle of input clock
Rise/Fall time of input clocks
Differential input voltage swing
Input clock jitter (cycle-to-cycle)
Unit Interval
Minimum Tx Eye Width
Maximum time between the jitter median and maximum
deviation from the median
D+ / D- Tx output rise/fall time
Minimum time in idle
Maximum time to transition to a valid Idle after sending
an Idle ordered set
Maximum time to transition from valid idle to diff data
Transmitter data skew between any 2 lanes
Time from asserting Beacon TxEn to beacon being trans-
mitted on the lane
Unit Interval
Minimum Receiver Eye Width (jitter tolerance)
Description
Description
Table 9 PCIe AC Timing Characteristics (Part 1 of 2)
3
Table 8 Input Clock Requirements
8 of 30
Min
399.88
399.88
Min
100
0.6
0.7
0.4
40
50
50
1
Typical
Typical
400
500
400
90
30
50
.9
1
0.2*RCUI
Max
400.12
400.12
Max
1300
0.15
125
20
20
80
1.6
60
1
January 25, 2011
Units
Unit
RCUI
MHz
ps
UI
UI
ps
UI
UI
UI
ps
ns
ps
UI
ps
%
V
2