IDT89HPES8T5AZBBCG8 IDT, Integrated Device Technology Inc, IDT89HPES8T5AZBBCG8 Datasheet

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IDT89HPES8T5AZBBCG8

Manufacturer Part Number
IDT89HPES8T5AZBBCG8
Description
IC PCI SW 8LANE 5PORT 196-CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT89HPES8T5AZBBCG8

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89HPES8T5AZBBCG8

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Part Number:
IDT89HPES8T5AZBBCG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Device Overview
Express switching solutions. The PES8T5A is an 8-lane, 5-port periph-
eral chip that performs PCI Express Base switching. It provides connec-
tivity and switching functions between a PCI Express upstream port and
up to four downstream ports and supports switching between down-
stream ports.
Features
Block Diagram
© 2009 Integrated Device Technology, Inc.
The 89HPES8T5A is a member of IDT’s PRECISE™ family of PCI
High Performance PCI Express Switch
– Eight 2.5Gbps PCI Express lanes
– Five switch ports
– Upstream port is x4
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
Legacy Support
– PCI compatible INTx emulation
– Bus locking
Transaction Layer
Data Link Layer
Mux / Demux
(Port 0)
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
Transaction Layer
Data Link Layer
Mux / Demux
(Port 2)
SerDes
Logical
8-Lane 5-Port
PCI Express® Switch
Layer
Phy
5-Port Switch Core / 8 PCI Express Lanes
Route Table
Figure 1 Internal Block Diagram
Transaction Layer
1 of 29
Data Link Layer
Mux / Demux
(Port 3)
SerDes
Logical
Layer
Phy
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Power Management
Testability and Debug Features
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates eight 2.5 Gbps embedded SerDes with 8B/10B
– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
– Utilizes advanced low-power design techniques to achieve low
– Supports PCI Power Management Interface specification (PCI-
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Arbitration
Port
queueing
encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
boards
typical power consumption
PM 1.2)
fication, Revision 2.0 (ACPI) supporting active link state
Transaction Layer
Data Link Layer
Mux / Demux
(Port 4)
SerDes
Logical
Layer
Phy
Scheduler
Transaction Layer
89HPES8T5A
Data Link Layer
Mux / Demux
(Port 5)
SerDes
Data Sheet
Logical
Layer
Phy
May 7, 2009

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IDT89HPES8T5AZBBCG8 Summary of contents

Page 1

Device Overview The 89HPES8T5A is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES8T5A is an 8-lane, 5-port periph- eral chip that performs PCI Express Base switching. It provides connec- tivity and switching functions between ...

Page 2

IDT 89HPES8T5A Data Sheet ◆ 11 General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions ...

Page 3

IDT 89HPES8T5A Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and ...

Page 4

IDT 89HPES8T5A Data Sheet General Purpose Input/Output The PES8T5A provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output ...

Page 5

IDT 89HPES8T5A Data Sheet Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] Type Name/Description I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is ...

Page 6

IDT 89HPES8T5A Data Sheet Signal GPIO[7] GPIO[8] GPIO[9] GPIO[10] Signal APWRDISN CCLKDS CCLKUS MSMBSMODE PERSTN Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin ...

Page 7

IDT 89HPES8T5A Data Sheet Signal RSTHALT SWMODE[2:0] WAKEN Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description I Reset Halt. When this signal ...

Page 8

IDT 89HPES8T5A Data Sheet Pin Characteristics Note: Some input pads of the PES8T5A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

Page 9

IDT 89HPES8T5A Data Sheet Function System Pins EJTAG / JTAG 1. Schmitt Trigger Input (STI) Pin Name Type Buffer APWRDISN I LVTTL CCLKDS I CCLKUS I MSMBSMODE I PERSTN I RSTHALT I SWMODE[2:0] I WAKEN I/O JTAG_TCK I LVTTL JTAG_TDI ...

Page 10

IDT 89HPES8T5A Data Sheet Logic Diagram — PES8T5A Reference Clocks Serdes Input Port 0 Serdes Input Port 2 Serdes Input Port 3 Serdes Input Port 4 Serdes Input Port 5 Master SMBus Interface Slave SMBus Interface System Pins PEREFCLKP PEREFCLKN ...

Page 11

IDT 89HPES8T5A Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter PEREFCLK Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of ...

Page 12

IDT 89HPES8T5A Data Sheet Parameter T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ENTER TIME T Lane to lane input skew RX-SKEW 1. Minimum, Typical, and ...

Page 13

IDT 89HPES8T5A Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a ...

Page 14

IDT 89HPES8T5A Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power ...

Page 15

IDT 89HPES8T5A Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13. Maximum power is measured under the following conditions: 70°C Ambient, 85% ...

Page 16

IDT 89HPES8T5A Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V ...

Page 17

IDT 89HPES8T5A Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN ...

Page 18

IDT 89HPES8T5A Data Sheet Package Pinout — 196-BGA Signal Pinout for PES8T5A The following table lists the pin numbers and signal names for the PES8T5A device. Pin Function Alt Pin PE0RP03 ...

Page 19

IDT 89HPES8T5A Data Sheet Pin Function Alt Pin K11 V CORE L12 DD K12 V L13 SS K13 GPIO_08 L14 K14 GPIO_07 JTAG_TCK ...

Page 20

IDT 89HPES8T5A Data Sheet Power Pins V Core D11 E4 E10 E13 F10 Core H10 C12 H11 D4 J4 D10 ...

Page 21

IDT 89HPES8T5A Data Sheet Ground Pins A12 A14 B12 B14 C4 C5 C11 C13 D12 E11 E14 F5 F8 F14 G4 G6 ...

Page 22

IDT 89HPES8T5A Data Sheet Signals Listed Alphabetically Signal Name APWRDISN CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 ...

Page 23

IDT 89HPES8T5A Data Sheet Signal Name PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PE4RN00 PE4RP00 PE4TN00 PE4TP00 PE5RN00 PE5RP00 PE5TN00 PE5TP00 PEREFCLKN PEREFCLKP PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK ...

Page 24

IDT 89HPES8T5A Data Sheet Signal Name SWMODE_0 SWMODE_1 SWMODE_2 WAKEN V CORE APE I/O Type Location I C14 I D14 I D13 I/O C1 See Table ...

Page 25

IDT 89HPES8T5A Data Sheet PES8T5A Pinout — Top View Core (Power I/O (Power ...

Page 26

IDT 89HPES8T5A Data Sheet PES8T5A Package Drawing — 196-Pin BC196/BCG196 May 7, 2009 ...

Page 27

IDT 89HPES8T5A Data Sheet PES8T5A Package Drawing — Page Two May 7, 2009 ...

Page 28

IDT 89HPES8T5A Data Sheet Revision History March 31, 2008: Publication of final data sheet. August 6, 2008: Added industrial temperature information to Tables 14 and 16 and to Ordering Information section. May 7, 2009: Revised labels in Table 15, Power ...

Page 29

IDT 89HPES8T5A Data Sheet Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations 89HPES8T5AZBBC 196-pin BC196 package, Commercial Temperature 89HPES8T5AZBBCG 196-pin Green BCG196 package, Commercial Temperature 89HPES8T5AZBBCI 196-pin BC196 package, Industrial Temperature 89HPES8T5AZBBCGI 196-pin Green BCG196 ...

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