IDT89HPES24T3G2ZCAL8 IDT, Integrated Device Technology Inc, IDT89HPES24T3G2ZCAL8 Datasheet - Page 3

• Manufacturer Part Number: IDT89HPES24T3G2ZCAL8
• Description: IC PCI SW 24LANE 3PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES24T3G2ZCAL8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES24T3G2ZCAL8

3(a), the master and slave SMBuses are tied together and the PES24T3G2 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES24T3G2 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES24T3G2 may be configured to operate in a split configuration as shown in Figure 3(b).
The PES24T3G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
Hot-Plug Interface
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES24T3G2 generates an SMBus transaction to the I/O expander with the
new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN
input pin (alternate function of GPIO) of the PES24T3G2. In response to an I/O expander interrupt, the PES24T3G2 generates an SMBus transaction
to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Many
GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configura-
tion EEPROM.
IDT 89HPES24T3G2 Data Sheet
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES24T3G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24T3G2
The PES24T3G2 provides General Purpose Input/Output (GPIO) pins (7 pins in the 19mm package and 11 pins in the 27mm package) that may be
PES24T3G2
(a) Unified Configuration and Management Bus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Table 1 Master and Slave SMBus Address Assignment for 27x27mm Package
Processor
SMBus
Master
Bit
1
2
3
4
5
6
7
EEPROM
Figure 3 SMBus Interface Configuration Examples
Serial
...
Devices
SMBus
Other
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
SSMBADDR[5]
Address
SMBus
Slave
3 of 48
0
1
1
(b) Split Configuration and Management Buses
PES24T3G2
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
Address
Master
SMBus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
1
0
1
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
September 29, 2010