IDT72V51553L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51553L7-5BB8 Datasheet
IDT72V51553L7-5BB8
Specifications of IDT72V51553L7-5BB8
Related parts for IDT72V51553L7-5BB8
IDT72V51553L7-5BB8 Summary of contents
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FEATURES: • • • • • Choose from among the following memory density options: IDT72V51543 Total Available Memory = 1,179,648 bits IDT72V51553 Total Available Memory = 2,359,296 bits • • ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits DESCRIPTION: The IDT72V51543/72V51553 multi-queue flow-control devices are single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup. All queues within ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits WCLK WEN 8 WRADD Write Control WADEN Logic Write Pointers PAF FSTR 8 General Flag PAFn Monitor FSYNC FXO FXI FF Active Q Flags PAF ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN CONFIGURATION A1 BALL PAD CORNER A D14 D13 D12 D10 B D15 D16 D11 D9 C D17 GND GND D8 D GND GND GND ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits DETAILED DESCRIPTION MULTI-QUEUE STRUCTURE The IDT multi-queue flow-control device has a single data input port and single data output port with FIFO ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits 18 deep within the IDT72V51553, each queue being setup within a single device utilizing all memory blocks available to produce a single queue. This is ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS Symbol Name I/O TYPE D[17:0] Data Input Bus LVTTL Din INPUT DF (1) Default Flag LVTTL INPUT DFM (1) Default Mode LVTTL INPUT ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE PAFn Bus Sync FSYNC LVTTL OUTPUT during Polled operation of the PAFn bus. During Polled operation each quadrant ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE PAE Programmable LVTTL Almost-Empty Flag OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE RDADD Read Address Bus LVTTL [7:0] INPUT (Continued) REN Read Enable LVTTL INPUT SCLK Serial Clock LVTTL INPUT ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE TDO (2) JTAG Test Data LVTTL Output OUTPUT operation, test data serially loaded output via the TDO on ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTE: 1. Stresses ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits AC TEST LOADS I/O Figure 2a. AC Test Load AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference ...
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... Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. 2. Values guaranteed by design, not currently tested. = 3.3V ± 0.15V 40°C to +85°C; JEDEC JESD8-A compliant Commercial Com'l & Ind'l IDT72V51543L6 IDT72V51543L7-5 IDT72V51553L6 IDT72V51553L7-5 Min. Max. Min. — 166 — 0.6 3.7 0.6 6 — ...
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... Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. 2. Values guaranteed by design, not currently tested. = 3.3V ± 0.15V 40°C to +85°C; JEDEC JESD8-A compliant Commercial Com'l & Ind'l IDT72V51543L6 IDT72V51543L7-5 IDT72V51553L6 IDT72V51553L7-5 Min. Max. Min. 0.6 3.7 0.6 0.6 3.7 0.6 0.6 3 ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits FUNCTIONAL DESCRIPTION MASTER RESET A Master Reset is performed by toggling the MRS input from HIGH to LOW to HIGH. During a master reset all ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits required for the device to load its internal setup registers. When a single multi- queue is used, the completion of device programming is signaled by ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits READ QUEUE SELECTION & READ OPERATION The multi-queue flow-control device has queues that data is read from via a common read port ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits NULL QUEUE OPERATION (OF THE READ PORT) Pipelining of data to the output port enables the device to provide 100% bus utilization in standard mode. ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits When queues within a single device are selected for write operations, the FF flag output of that device will maintain control of the FF flag ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits duplicate of the PAF flag on the PAF[7:0] flag bus, this will be discussed in detail in a later section of the data sheet. See ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING Output Valid, OV Flag Boundary I/O Set-Up OV Goes LOW after 1 In18 to out18 or In9 ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED) Programmable Almost Empty Flag, PAE Boundary I/O Set-Up In18 to out18 or In9 to out9 (Both ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PAFn FLAG BUS OPERATION The IDT72V51543/72V51553 multi-queue flow-control devices can be configured for queues, each queue having its own almost full status. ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits the new quadrant selected 1 RCLK cycle after quadrant selection. PAEn[0:7] gets status of queues, Queue[0:7] respectively. To address the second quadrant, Queue[8:15], the RDADD ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits MRS t RSS WEN REN t RSS SENI t RSS FSTR, ESTR t RSS WADEN, RADEN t RSS ID0, ID1, ID2 t RSS OW, IW ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits w-2 WCLK t QS WADEN WEN t AS WRADD Qx FF PAF Active Bus PAF-Qx (5) PRS RCLK REN t QS RADEN t AS RDADD ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 29 TEMPERATURE RANGES ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 30 TEMPERATURE RANGES ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 31 TEMPERATURE RANGES ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits WCLK t ENS WEN RCLK REN Qout Last Word Read Out of Queue OV NOTES has previously ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 33 TEMPERATURE RANGES ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 34 TEMPERATURE RANGES ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* *B* RCLK t ENS REN RDADD RADEN Qout (Device 1) OV HIGH-Z ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* *B* RCLK t t ENS ENH REN t AS RDADD t QS RADEN OUT ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits NULL QUEUE RCLK t AS RDADD t QS RADEN REN t A Qout Q1 Wn-3 Q1 Wn-2 OV NOTES: 1. The purpose of the Null ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* WCLK WEN WRADD WADEN Din PAF HIGH-Z (Device 1) PAF (Device 2) ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* *B* RCLK REN HIGH RDADD RADEN HIGH-Z Qout PAE HIGH-Z (Device 1) ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits RCLK Device 1 Quadrant 2 RDADD 001xxx10 t t STS STH ESTR PAEn NOTES: 1. Quadrants can be selected on consecutive ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* WCLK WADEN FSTR t ENS WEN WRADD D5Q24 100 11000 Wp Dn Writes to Previous Q ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* RCLK RADEN ESTR REN RDADD D0Q31 000 11111 OE t OLZ Qout W Prev. Q WCLK ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 43 TEMPERATURE RANGES ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 44 TEMPERATURE RANGES ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits Serial Programming Data Input Serial Enable Data Bus Write Clock Write Enable Write Queue Select Write Address Full Strobe Programmable Almost Full Full Sync1 Full ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V51543/72V51553 incorporates the necessary ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits 1 0 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects ...
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IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits t 1 TCK t 3 TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t DO (1) ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. DATASHEET DOCUMENT HISTORY 10/12/2001 pgs ...