IDT72P51339L6BB IDT, Integrated Device Technology Inc, IDT72P51339L6BB Datasheet - Page 43

• Manufacturer Part Number: IDT72P51339L6BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51339L6BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51339L6BB

is only pertinent to the queue being selected for read operations at that time.
Remember, that when in expansion configuration only one multi-queue device
can be read from at any moment in time, thus the EF flag provides status of the
active queue on the read port.
output have a High-Impedance capability, such that when a queue selection is
made only a single device drives the EF flag bus and all other EF flag outputs
connected to the EF flag bus are placed into High-Impedance. The user does
not have to select this High-Impedance state, a given multi-queue flow-control
device will automatically place its EF flag output into High-Impedance when none
of its queues are selected for read operations.
flag output of that device will maintain control of the EF flag bus. Its EF flag will
simply update between queue switches to show the respective queue status.
on the 1-3 bit ID code (1 if two multi-queue are configured with a maximum total
of 256 queues, 2 if four devices are used totalling a maximum of 256 queues,
and 3 if there are up to eight devices with a maximum total of 256 queues) found
in the 3 most significant bits of the read queue address bus, RDADD. If the 3 most
significant bits of RDADD match the 1-3 bit ID code setup on the static inputs, ID0,
ID1 and ID2 then the EF flag output of the respective device will be in a Low-
Impedance state. If they do not match, then the EF flag output of the respective
device will be in a High-Impedance state. See Figure 51, Output Ready Flag
Timing for details of flag operation, including when more than one device is
connected in expansion.
ALMOST FULL FLAG
single Programmable Almost Full flag output, PAF. The PAF flag output provides
a status of the almost full condition for the active queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitors and maintains a status of the almost full condition of all queues within
it, however only the queue that is selected for write operations has its full status
output to the PAF flag. This dedicated flag is often referred to as the “active queue
almost full flag”. The position of the PAF flag boundary within a queue can be
at any point within that queues depth. This location can be user programmed
via the serial port or one of the default values (8 or 128) can be selected if the
user has performed default programming.
full status, when a queue is selected on the write port, this status is output via the
PAF flag. The PAF flag value for each queue is programmed during multi-queue
device programming (along with the number of queues, queue depths and
almost empty values). The PAF offset value, m, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAF value of different queues within the same device
can be different values.
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same WCLK cycle
that data can actually be written to the new queue. That is, a new queue can
be selected on the write port via the WRADD bus, WADEN enable and a rising
edge of WCLK. On the third rising edge of WCLK following a queue selection,
the PAF flag output will show the full status of the newly selected queue. The PAF
is flag output is double register buffered, so when a write operation occurs at
the almost full boundary causing the selected queue status to go almost full the
PAF will go LOW 2 WCLK cycles after the write. The same is true when a read
occurs, there will be a 2 WCLK cycle delay after the read operation.
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
This connection of flag outputs to create a single flag requires that the EF flag
When queues within a single device are selected for read operations, the EF
The multi-queue device places its EF flag output into High-Impedance based
As previously mentioned the multi-queue flow-control device provides a
As mentioned, every queue within a multi-queue device has its own almost
When queue switches are being made on the write port, the PAF flag output
43
t
t
occur based on a rising edge of WCLK. Internally the multi-queue device
monitors and keeps a record of the almost full status for all queues. It is possible
that the status of a PAF flag maybe changing internally even though that flag is
not the active queue flag (selected on the write port). A queue selected on the
read port may experience a change of its internal almost full flag status based
on read operations. The multi-queue flow-control device also provides a
duplicate of the PAF flag on the PAF[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
ALMOST EMPTY FLAG
single Programmable Almost Empty flag output, PAE. The PAE flag output
provides a status of the almost empty condition for the active queue currently
selected on the read port for read operations. Internally the multi-queue flow-
control device monitors and maintains a status of the almost empty condition of
all queues within it, however only the queue that is selected for read operations
has its empty status output to the PAE flag. This dedicated flag is often referred
to as the “active queue almost empty flag”. The position of the PAE flag boundary
within a queue can be at any point within that queues depth. This location can
be user programmed via the serial port or one of the default values (8 or 128)
can be selected if the user has performed default programming.
empty status, when a queue is selected on the read port, this status is output via
the PAE flag. The PAE flag value for each queue is programmed during multi-
queue device programming (along with the number of queues, queue depths
and almost full values). The PAE offset value, n, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAE value of different queues within the same device
can be different values.
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same RCLK cycle
that data actually falls through to the output register from the new queue. That
is, a new queue can be selected on the read port via the RDADD bus, RADEN
enable and a rising edge of RCLK. On the third rising edge of RCLK following
a queue selection, the data word from the new queue will be available at the
output register and the PAE flag output will show the empty status of the newly
selected queue. The PAE is flag output is double register buffered, so when a
read operation occurs at the almost empty boundary causing the selected queue
status to go almost empty the PAE will go LOW 2 RCLK cycles after the read.
The same is true when a write occurs, there will be a 3 RCLK cycle delay after
the write operation.
t
t
occur based on a rising edge of RCLK. Internally the multi-queue device
monitors and keeps a record of the almost empty status for all queues. It is possible
that the status of a PAE flag maybe changing internally even though that flag is
not the active queue flag (selected on the read port). A queue selected on the
WAF.
WAF.
RAE
RAE.
So the PAF flag delay from a write operation to PAF flag LOW is 2 WCLK +
Note, if t
The PAF flag is synchronous to the WCLK and all transitions of the PAF flag
See Figures 23 and 24 for Almost Full flag timing and queue switching.
As previously mentioned the multi-queue flow-control device provides a
As mentioned, every queue within a multi-queue device has its own almost
When queue switches are being made on the read port, the PAE flag output
So the PAE flag delay from a read operation to PAE flag LOW is 2 RCLK +
Note, if t
The PAE flag is synchronous to the RCLK and all transitions of the PAE flag
. The delay from a write operation to PAE flag HIGH is t
The delay from a read operation to PAF flag HIGH is t
SKEW
SKEW
is violated there will be one added WCLK cycle delay.
is violated there will be one added RCLK cycle delay.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AUGUST 4, 2005
SKEW2
SKEW2
+ WCLK +
+ RCLK +