IDT89HPES48T12ZABR IDT, Integrated Device Technology Inc, IDT89HPES48T12ZABR Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES48T12ZABR
• Description: IC PCI SW 48LANE 12PORT 1156BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES48T12ZABR

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: FCBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES48T12ZABR

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ-
ential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
IDT 89HPES48T12 Data Sheet
The following tables lists the functions of the pins provided on the PES48T12. Some of the functions listed may be multiplexed onto the same pin.
PE0RN[3:0]
PE1RN[3:0]
PE2RN[3:0]
PE3RN[3:0]
PE4RN[3:0]
PE5RN[3:0]
PE6RN[3:0]
PE7RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE2RP[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3TP[3:0]
PE3TN[3:0]
PE4RP[3:0]
PE4TP[3:0]
PE4TN[3:0]
PE5RP[3:0]
PE5TP[3:0]
PE5TN[3:0]
PE6RP[3:0]
PE6TP[3:0]
PE6TN[3:0]
PE7RP[3:0]
Signal
Type
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Table 2 PCI Express Interface Pins (Part 1 of 2)
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for
port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for
port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for
port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs
for lanes 4 through 7.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for
port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs
for lanes 4 through 7.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for
port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for
port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for
port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs
for lanes 4 through 7.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for
port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs
for lanes 4 through 7.
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for
port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for
port 4.
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for
port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs
for lanes 4 through 7.
PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for
port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs
for lanes 4 through 7.
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for
port 6.
PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for
port 6.
PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for
port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs
for lanes 4 through 7.
4 of 47
Name/Description
October 7, 2008