IDT89HPES34H16ZABLI IDT, Integrated Device Technology Inc, IDT89HPES34H16ZABLI Datasheet - Page 5

• Manufacturer Part Number: IDT89HPES34H16ZABLI
• Description: IC PCI SW 34LANE 16PORT 1156FBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES34H16ZABLI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES34H16ZABLI

IDT 89HPES34H16 Data Sheet
SSMBADDR[5,3:1]
PEREFCLKN[3:0]
PEREFCLKP[3:0]
MSMBADDR[4:1]
PE13RP[0]
PE13RN[0]
PE14RP[0]
PE14RN[0]
PE15RP[0]
PE15RN[0]
MSMBCLK
MSMBDAT
PE13TP[0]
PE13TN[0]
PE14TP[0]
PE14TN[0]
PE15TP[0]
PE15TN[0]
REFCLKM
SSMBCLK
SSMBDAT
Signal
Signal
Type
Type
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
I
Table 2 PCI Express Interface Pins (Part 3 of 3)
PCI Express Port 13 Serial Data Receive. Differential PCI Express receive pair for
port 13.
PCI Express Port 13 Serial Data Transmit. Differential PCI Express transmit pair for
port 13. W
PCI Express Port 14 Serial Data Receive. Differential PCI Express receive pair for
port 14.
PCI Express Port 14 Serial Data Transmit. Differential PCI Express transmit pair for
port 14.
PCI Express Port 15 Serial Data Receive. Differential PCI Express receive pair for
port 15.
PCI Express Port 15 Serial Data Transmit. Differential PCI Express transmit pair for
port 15.
PCI Express Reference Clock Mode Select. This signal selects the frequency of the
reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
PCI Express Reference Clock. Differential reference clock pair input. This clock is
used as the reference clock by on-chip PLLs to generate the clocks required for the
system logic and on-chip SerDes. The frequency of the differential reference clock is
determined by the REFCLKM signal.
Master SMBus Address. These pins determine the SMBus address of the serial
EEPROM from which configuration information is loaded.
Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the
master SMBus. It is active and generating the clock only when the EEPROM or I/O
Expanders are being accessed.
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
Slave SMBus Address. These pins determine the SMBus address to which the slave
SMBus interface responds.
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the
slave SMBus.
Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.
Table 3 SMBus Interface Pins
5 of 45
Name/Description
Name/Description
October 21, 2009