IDT88P8342BHI IDT, Integrated Device Technology Inc, IDT88P8342BHI Datasheet
IDT88P8342BHI
Specifications of IDT88P8342BHI
Related parts for IDT88P8342BHI
IDT88P8342BHI Summary of contents
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FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors - Fragment and burst length ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Features ........................................................................................................................................................................................................................ 1 Applications .................................................................................................................................................................................................................. 1 1. Introduction ............................................................................................................................................................................................................. 8 2. Pin description ......................................................................................................................................................................................................... 9 3. External interfaces ................................................................................................................................................................................................. 13 3.1 SPI-3 ............................................................................................................................................................................................................... 13 3.1.1 SPI-3 ingress ........................................................................................................................................................................................ 13 3.1.2 SPI-3 egress ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Table of Contents (Continued) 9.3 Indirect registers for SPI-3A and SPI-3B modules ............................................................................................................................................. 56 9.3.1 Block base 0x0000 registers ................................................................................................................................................................. 57 9.3.2 Block base 0x0200 registers ................................................................................................................................................................. 57 9.3.3 Block base 0x0500 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Figure 1. Typical application: optical port and two NPUs ................................................................................................................................................... 8 Figure 2. Data Path Diagram ........................................................................................................................................................................................... 8 Figure 3. Link mode SPI-3 ingress interface ................................................................................................................................................................... 14 Figure 4. PHY mode SPI-3 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Table 1 – I/O types .......................................................................................................................................................................................................... 9 Table 2 – SPI-3 ingress interface pin definition .................................................................................................................................................................. 9 Table 3 – SPI-3 egress interface pin definition ................................................................................................................................................................ 10 Table 4 – SPI-3 status ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 List of Tables (Continued) Table 57 - SPI-3 egress test register (register_offset=0x02) ............................................................................................................................................ 59 Table 58 - SPI-3 egress fill level register (register_offset=0x03) ...................................................................................................................................... 60 Table 59 - SPI-3 egress max fill ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 List of Tables (Continued) Table 112 - SPI-4 ingress bit alignment counter register (0x02 to 0x0B) ......................................................................................................................... 75 Table 113 - SPI-4 ingress manual alignment phase/result register (0x0C to 0x1F) .......................................................................................................... 75 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 TYPICAL APPLICATION Exchange between optical ports and two NPU/Traffic Managers OC-48/ 4xOC-12/ 16xOC-3 Multi-Rate SONET Framer 1. INTRODUCTION The IDT88P8342 device is a dual SPI-3 to single SPI-4 exchange intended for use ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 2. PIN DESCRIPTION SPI-3 (two instantiations) For the SPI-3 interfaces, each pin is used differently depending whether the SPI Link mode or in PHY mode. Each of the SPI-3 interfaces ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 TABLE 3 – SPI-3 EGRESS INTERFACE PIN DEFINITION Generic Name Specific Name E_FCLK SPI3A_E_FCLK SPI3B_E_FCLK E_ENB SPI3A_E_ENB SPI3B_E_ENB E_DAT[31:0] SPI3A_E_DAT[31:0] SPI3B_E_DAT[31:0] E_MOD[1:0] SPI3A_E_MOD[1:0] SPI3B_E_MOD[1:0] E_PRTY SPI3A_E_PRTY SPI3B_E_PRTY E_SOP SPI3A_E_SOP SPI3B_E_SOP E_EOP SPI3A_E_EOP ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-4 (one instantiation) For the SPI-4 interface, each pin is used differently depending whether the SPI Link mode or in PHY mode. The pin is given a generic name, shown ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Parallel microprocessor Interface The Parallel microprocessor interface is configurable to work in Intel or Motorola modes. Be sure to connect SPI_EN to a logic low when using the parallel microprocessor interface mode. ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 3. EXTERNAL INTERFACES The external interfaces provided on the IDT88P8342 device are two SPI- 3 interfaces, one SPI-4 interface, a serial or parallel microprocessor interface, a JTAG interface, and a set of ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-3 ingress Link mode Refer to [Glossary] for details about the SPI-3 interface. • The PHY pushes data into the device in blocks from 256 bytes. • The SPI ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 3.1.2 SPI-3 egress - All fragments will programmable equal length with the exception of EOP fragment which may be shorter LID to LP map - 64 entries, one per ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-3 egress Link mode The SPI Exchange receives status information from the PHY. The PHY indicates its ability to receive data. Status information for all logical ports is directed towards the packet ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 3.2 SPI-4 Refer to OIF SPI-4 document (see Glossary) for full details of the implemen- tation agreement. - Clock rate 400 MHz (160 - 800MHz DDR) - Link and ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Data sampling The I_LOW field in the Table 89 SPI-4 ingress configuration register (Block_base 0x0300 + Register_offset 0x00) selects an operating mode between 80 MHz and 200 MHz or between 200 MHz ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Manual phase selection The automatic phase adjustment can be overruled by the processor when the FORCE flag is set see Table 99, SPI-4 ingress bit alignment control register (register_offset 0x11). The PHASE_ASSIGN ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 • Normal status information when in the IN_SYNCH state The normal status information is generated based on ingress buffer full information and PFP buffer segment fill level. For information on DIP-2 generation ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-4 egress status channel Status channel bit alignment The bit alignment algorithm for the status channel is the same as was described for the data channel. Status Channel Frame synchronization A= a ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 3.3 Microprocessor interface - Parallel microprocessor interface • 8 bit data bus for parallel operation • Byte access • Direct accessed space • Indirect access space is used for most registers • ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 4. DATAPATH AND FLOW CONTROL The following sections describe the datapaths through the device. The datapaths shown are as follows: - SPI-3A <-> SPI-4 - SPI-3B <-> SPI-4 - SPI-3A <-> SPI-3B ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 DATAPATH CONFIGURATION A logical view of datapath configuration using Packet Fragment Processors is shown in Figure 12, Logical View of Datapath Configuration Using PFPs. Two PFPs are associated with each SPI-3 port, ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 4.1 SPI-3 to SPI-4 datapath and flow control Two packet fragment processor modules from SPI-3 to SPI-4 are provided. One packet fragment processor module is associated with one SPI-3 ingress interface. Both ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Erroneous operation SPI-3 ingress buffers marked with an address parity error are always immediately flushed. A SPI-3 flush event is generated. Store process The process parameters are stored in a descriptor table. ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-4 egress data bursts The PFP produces fragments N*16 bytes defined by the MAX_BURST_H or MAX_BURST_S parameter associated with each LID. For a high priority (starving) LID ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-4 egress interface port associated control The SPI-4 interface has an associated LID to LP map (See Table 101 - SPI- 4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-3 ingress to SPI-4 egress flow control For control information there are two separate cases to consider: The case that the SPI-3 physical interface port is configured in Link mode, and the ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 4.2 SPI-4 to SPI-3 datapath and flow control Two Packet Fragment Processor modules from SPI4 ingress to SPI-3 egress are provided, all connected to one SPI-4 ingress interface. Packet bursts from the ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-4 ingress interface configurable parameters: The IDT88P8342 can interface to either a Link or a PHY layer device. The SPI-4 port can be enabled or disabled. The SPI-4 ingress bits are aligned ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-4 ingress to SPI-3 egress flow control The SPI-4 control information is transmitted to the adjacent device. The adjacent device determines which LP to service next according to the status information it ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 4.3 SPI-3 ingress to SPI-3 egress datapath The SPI-3 redirect buffer can store SPI-3 packet fragments. The status of the packet fragment buffers is forwarded to the associated packet fragment proces- sor. ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 4.4 Microprocessor interface to SPI-3 datapath capture/insert configurable parameters Enable insertion / capture of data to the SPI-3 or SPI-4 data stream (which is dependent on the egress control register). For each ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 4.4.2 Microprocessor insert to SPI-3 egress datapath The diagram below shows the datapath through the device from the microprocessor data insert interface to a SPI-3 egress port. The following is a description ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 4.4.3 Microprocessor interface to SPI-4 egress datapath Packets can be inserted into the SPI-3-4 datapath by the microprocessor. The following is a description of the path taken by a burst of data ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 4.4.4 SPI-4 ingress to microprocessor interface datapath The diagram below shows the datapath through the device from the SPI-4 interface to the microprocessor data capture interface. The following is a description of ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 5. PERFORMANCE MONITOR AND DIAGNOSTICS 5.1 Mode of operation A performance monitor & diagnostics module is available in modules A and B. The performance monitor captures events and accumulates error events and ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 6. CLOCK GENERATOR The device generates clocks from the SPI-4 ingress clock (I_DCLK) or from the REF_CLK input pin. The clock so selected is used for core functions of the device, and ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 7. LOOPBACKS Local loopbacks are supported on both of the SPI-3 physical ports. They are described below SPI-3 8 bit / 32 bit Min: 19.44MHz Max: 133MHz 7.1 SPI-3 Loopback ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 8. OPERATION GUIDE 8.1 Hardware operation 8.1.1 System reset There are two methods for resetting the device: hardware reset & software reset. During reset the output clocks are not toggled. Hardware reset ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 2) Configure the clock generator as follows: a) Configure the value for the MCLK divider, OCLK dividers and enables in the Clock Generator Control Register (refer to Table 121, Clock generator control ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 8.2.5 SPI-4 status channel software The SPI-4 status channel may be configured to either TTL or LVDS by loading the appropriate status channel binary file to activate the firmware. Download LVTTL.bin when ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 example, a SPI-4 clock of 400 MHz gives a data unit interval of 1.25 ns, so match the lengths within the entire signal group to within 625 ps inches. 3) ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 For an ideal case, there is zero jitter on clock an data, zero skew, the clock high and low level phase are symmetrical. For random input data on each lane, the counters ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9. REGISTER DESCRIPTION There are two distinctly different types of register access in the IDT88P8342. Direct access registers are used for interrupts and other high-priority registers and for access to the indirect ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 TABLE 20 - BIT ORDER WITHIN A 16-BIT ADDRESS REGISTER Indirect High Address (register 0x35) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Bit ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 TABLE 24 - INDIRECT ACCESS BLOCK BASES FOR COMMON MODULE Block_base 0x0000 SPI-4 ingress LP to LID tables 0x0100 SPI-4 ingress calendar_0 0x0200 SPI-4 ingress calendar_1 0x0300 SPI-4 ingress registers 0x0400 SPI-4 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 ERROR code See Table 28, Error coding. This error code pertains to the last indirect access attempted. TABLE 28 - ERROR CODING TABLE ERROR code Error Meaning 0x00 Normal indirect access completion ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.2 Direct access registers The direct access registers are in the directly-addressed access space. Direct access registers are more quickly accessed, and serve the needs of interrupts and the indirect access registers. ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-4 data insert control register TABLE 33 - SPI-4 DATA INSERT CONTROL REGISTER (REGISTERS 0x02 and 0x0A) Field Bits Length DATA_AVAILABLE 0 Reserved 7:1 A SPI-4 data insert control register has read ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Software reset TABLE 39 - SOFTWARE RESET REGISTER (0x20 in the direct accessed space) Field Bits Length SW_RESET 0 1 INIT_DONE 1 1 Reserved 7:2 6 The software reset bit is writable ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 I_BUS_ERR_EN SPI-4 ingress bus error interrupt indication enable. 0=Disable bus error interrupt 1=Enable bus error interrupt SPI4_INACTIVE_TRANSFER_EN SPI-4 ingress inactive transfer inter- rupt indication enable. 0=Disable inactive transfer interrupt 1=Enable inactive transfer ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-43_INSERT_EN SPI-4 ingress to SPI-3 egress insert event interrupt enable. 0=Disable insert interrupt 1=Enable insert interrupt PMON_EN Performance Monitor event interrupt enable. 0=Disable PMON interrupt 1=Enable PMON interrupt Primary interrupt status register ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Primary interrupt enable register (0x2E in the direct accessed space) TABLE 46 - PRIMARY INTERRUPT ENABLE REGIS- TER (0x2E IN THE DIRECT ACCESSED SPACE) Field Bits MODULE_A_EN 0 MODULE_B_EN 1 Reserved 2 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.3 Indirect registers for SPI-3A and SPI-3B modules Module Module_base 0x0000 Module Module_base 0x2000 TABLE 48 - MODULE A/B INDIRECT REGISTER Table Number, Page Block_base, Register_offset ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.3.1 Block base 0x0000 registers SPI-3 ingress LP to LID map (Block_base 0x0000 + Register_offset 0x00 to 0xFF) TABLE 49 - SPI-3 INGRESS LP TO LID MAP Field Bits Length LID 5:0 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 EVEN_PARITY A SPI-3 interface is provisioned to generate and to check for odd or even parity. The PARITY_EN bit must be set for this to become effective. Odd parity is standard for ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 LP The LP programmed is associated to the LID with the same number as the register address. ENABLE This bit is used to enable or disable the connection of a LID to ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 the DAT_PAR_ERR bit field. The LP affected by these two parity error bit fields is enumerated in the PORT_ADDRESS field. The bit fields of SPI-3 egress test register are described. The bit ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Performance monitor counters Two categories of events are captured: LID and non LID associated events least one event is captured in one of the interrupt indication registers, an active PMON ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Non LID associated interrupt indication register (Block_base 0x0C00 + Register_offset 0x0C) TABLE 62 - NON LID ASSOCIATED INTERRUPT INDICATION REGISTER (REGISTER_OFFSET 0x0C) Field Bits Length SPI4_LOCK_UN 0 SPI3_LOCK_UN 1 SPI3_ICLK_UN 2 SPI3_ECLK_UN ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Non critical LID associated capture table (Block_base 0x0C00 + Register_offset 0x10-0x15) TABLE 66 - NON CRITICAL LID ASSOCIATED CAPTURE TABLE (REGISTER_OFFSET 0x10-0x15) Register EVENT_TYPE 0x00 Inactive ingress SPI-3 logical port event 0x01 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.3.7 Block base 0x0100 registers SPI-3 ingress packet length configuration register (Block_base 0x1000 + Register_offset 0x00-0x3F) TABLE 72 - SPI-3 INGRESS PACKET LENGTH CONFIGURATION REGISTER Field Bits Length MIN_LENGTH 7:0 Reserved 15:8 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 FREE_SEGMENT The FREE_SEGMNET field is used to define the SPI- 3 ingress per-LID free segment backpressure threshold based on the number of free buffer segments (M) available, as follows: THRESHOLD = N ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.3.11 Block base 0x1600 registers The SPI-4 ingress registers are at Block_base 0x1600. SPI-4 ingress packet length configuration (Block_base 0x1600 + Register_offset 0x00-0x3F) TABLE 79 - SPI-4 INGRESS PACKET LENGTH CONFIGURATION (64 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.3.14 Block base 0x1900 registers SPI-4 to SPI-3 PFP register (Block_base 0x1900 + Register_Offset 0x00) TABLE 83 - SPI-4 TO SPI-3 PFP REGISTER (0x00) Field Bits Length NR_LID 2:0 Reserved 7:3 The ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.4 Common module indirect registers (Module_base 0x8000) TABLE 85 -COMMON MODULE (MODULE_BASE 0x8000) INDIRECT REGISTER TABLE Table Number, Page Block_base, Register_offset 86, page 69 0x0000, 0x00-0xFF 87, page 69 0x0100, 0x00-0xFF 88, ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.4.1 Common module block base 0x0000 registers SPI-4 ingress LP to LID maps (Block_base 0x0000 + Register_offset 0x00 to 0xFF) TABLE 86 - SPI-4 INGRESS LP TO LID MAP (256 ENTRIES, ONE ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 I_CLK_EDGE The SPI-4 ingress LVTTL status clock active clock edge is selected using the I_CLK_EDGE field. 0=SPI-4 ingress clock uses the rising edge 1= SPI-4 ingress clock uses the falling edge I_DSC ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 SPI-4 ingress calendar configuration register (Block_base 0x0300 + Register_offset 0x04 - 0x05) TABLE 93 - SPI-4 INGRESS CALENDAR CONFIGU- RATION REGISTER (0x04 to 0x05) Field Bits Length I_CAL_M 7:0 I_CAL_LEN 13:8 The ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 insert a DIP-2 error on the SPI-4 ingress status interface, and read the number of DIP-2 errors seen on the SPI-4 egress status interface. I_FORCE_TRAIN The I_FORCE_TRAIN field is used to force ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 maximum 256 LPs are needed on the SPI-4 interface, the calendar entries should be used for scheduling more frequent status updated for higher-speed LPs. The value of time-critical LPs must appear multiple ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 ALPHA The SPI-4 egress ALPHA field is the number of repetitions of the data training sequence that must be scheduled every DATA_MAX_T cycles. The value for alpha used is actually one more ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 DIP_2 The DIP_2 field is used to read the number of DIP-2 errors seen on the SPI-4 egress status interface. The DIP_2 field saturates at the value 0xFFFF, and is automatically cleared ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 DTCn [1:0] Used for adding 0.1 clock cycles of output delay to SPI- 4 egress data lane n. [1:0]=0=No added delay [1:0]=1=Add 0.1 clock cycle of delay to data lane n [1:0]=2=Add ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 9.4.10 Common module block base 0x0900 registers PMON timebase control register (Block_base 0x0900 + Register_offset 0x00) TABLE 119 - PMON TIMEBASE CONTROL REGIS- TER (REGISTER_OFFSET 0x00) Field Bits Length INTERNAL 0 TIMER ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 General purpose I/O (Block_base 0x0900 + Register_offset 0x20) TABLE 123 - GPIO REGISTER (REGISTER_OFFSET 0x20) Field Bits Length DIR_OUT 4:0 Reserved 7:5 LEVEL 12:8 Reserved 15:13 MONITOR_EN 20:16 Five general purpose I/O ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 10. JTAG INTERFACE The device supports the optional TRST input signal. It supports a TCK clock frequency up to 10MHz. TABLE 126 – JTAG INSTRUCTIONS Code Instruction 000 EXTEST 001 IDCODE 010 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 11.3 Terminal Capacitance TABLE 129 – TERMINAL CAPACITANCE Parameter Symbol Input Capacitance C I Load Capacitance C O Load Capacitance for OCLK C O [3:0] signals Load Capacitance for C O microprocessor ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 11.5 DC Electrical characteristics TABLE 131 – DC ELECTRICAL CHARACTERISTICS Parameter Description CMOS I/O V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 11.6 AC characteristics 11.6.1 SPI-3 I/O timing Refer to [SPI-3 in Glossary] for logical timing diagrams of the SPI-3 and SPI- 4 interfaces. Note that underclocking and overclocking for the SPI-4 and ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 11.6.2 SPI-4 LVDS Input / Output SPI-4 input and output timing is shown in the following paragraph. Double Data Rate protocol is used for data and status transfer. The SPI-4 LVDS signals ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 TABLE 133 – SPI-4.2 LVDS AC INPUT / OUTPUT TIMING SPECIFICATIONS Inputs Unit Min. Typ. Duty cycle % 45 50 Frequency (DDR) MHz 80 — Frequency (DDR) MHz 200 311 TR, TF ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 11.6.6.1 Microprocessor parallel port AC timing specifications Be sure to connect SPI_EN to a logic low when using the parallel µP interface mode. Read cycle specification Motorola non-multiplexed (MPM=0) DSB + CSB ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Write cycle specification Motorola non-multiplexed (MPM=0) DSB + CSB R/WB ADD[5:0] Write DBUS[7:0] Figure 38. Microprocessor parallel port Motorola write timing diagram TABLE 139 – MICROPROCESSOR PARALLEL PORT MOTOROLA WRITE TIMING Symbol ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Read cycle specification Intel non-multiplexed bus (MPM=1) CSB + RDB ADD[5:0] Read DBUS[7:0] : NOTE 1. WRB should be tied to High. Figure 39. Microprocessor parallel port Intel mode read timing diagram ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Write cycle specification Intel non-multiplexed bus (MPM=1) WRB + CSB ADD[5:0] Write DBUS[7:0] : NOTE 1. RDB should be tied to a logic one. Figure 40. Microprocessor parallel port Intel mode write ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 11.6.6.2 Serial microprocessor interface (serial peripheral interface mode) Timing Characteristics The maximum SPI Data transfer clock frequency is 2 MHz. The detail information of the timing characteristics is shown in below and ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 12. MECHANICAL CHARACTERISTICS 12.1 Device overview ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 12.2 Pin name/ball location table SIGNAL PIN NAME BALL SIGNAL PIN NAME SPI3B_E_DAT[21] A4 SPI3B_I_DAT[26] SPI3B_E_DAT[20] E5 SPI3B_I_DAT[25] SPI3B_E_DAT[19] B4 SPI3B_I_DAT[24] SPI3B_E_DAT[18] D4 SPI3B_I_DAT[23] SPI3B_E_DAT[17] A3 SPI3B_I_DAT[22] SPI3B_E_DAT[16] C4 SPI3B_I_DAT[21] SPI3B_E_DAT[15] B3 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 12.2. Pin name/ball location table (continued) SIGNAL PIN NAME BALL SIGNAL PIN NAME RESERVED RESERVED AK17 RESERVED] RESERVED AN16 RESERVED RESERVED AP16 RESERVED RESERVED AL17 RESERVED RESERVED AK18 RESERVED AM17 RESERVED RESERVED ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 12.2 Pin name/ball location table (continued) SIGNAL PIN NAME BALL SIGNAL PIN NAME SPI3A_E_DAT[2] SPI3A_E_DAT[29] A26 SPI3A_E_DAT[28] E25 SPI3A_E_DAT[1] SPI3A_E_DAT[27] D25 SPI3A_E_DAT[0] SPI3A_E_FCLK SPI3A_E_DAT[26] C25 SPI3A_PTPA SPI3A_E_DAT[25] A25 SPI3A_TADR[7] SPI3A_E_DAT[24] B25 SPI3A_TADR[6] ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 12.3 Device package The SPI Exchange IDT88P8342 device is packaged 820-ball one millimeter ball pitch thermally-enhanced plastic ball grid array. All balls, whether used or ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 Figure 43. IDT88P8342 820PBGA package, top and side views INDUSTRIAL TEMPERATURE RANGE 95 APRIL 10, 2006 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 13. GLOSSARY ACRONYM FIFO First In First Out memory LID Logical IDentifier See also Logical Port (LP) The entity associated with a flow of data between a SPI SPI-4 ...
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IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4 14. DATASHEET DOCUMENT REVISION HISTORY ISSUE DATE • 0.7 05/21/04 General Release • 0.8 10/01/04 AG30 ball location changed to SPI4_I_STAT_N[1] and AF31 ball location changed to SPI4_I_STAT_P[0] on Pin name/ball location ...
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ORDERING INFORMATION IDT X X Device Type Package NOTE: 1. Green parts are available. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X X Process / Temperature Range 88P8342 for SALES: 800-345-7015 or ...