ACPL-W70L-000E Avago Technologies US Inc., ACPL-W70L-000E Datasheet - Page 13

• Manufacturer Part Number: ACPL-W70L-000E
• Description: OPTOCOUPLER 2CH 15MBD CMOS 6SSOP
• Manufacturer: Avago Technologies US Inc.

Specifications of ACPL-W70L-000E

• Input Type: DC
• Package / Case: 6-SSOP
• Voltage - Isolation: 5000Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 10mA
• Data Rate: 15MBd
• Propagation Delay High - Low @ If: 23ns @ 6mA
• Current - Dc Forward (if): 10mA
• Output Type: Push-Pull, Totem-Pole
• Mounting Type: Surface Mount
• Isolation Voltage: 5000 Vrms
• Maximum Continuous Output Current: 10 mA
• Maximum Fall Time: 3.5 ns
• Maximum Forward Diode Current: 10 mA
• Maximum Rise Time: 3.5 ns
• Minimum Forward Diode Voltage: 1.2 V
• Output Device: Logic Gate Photo IC
• Configuration: 1 Channel
• Maximum Baud Rate: 15 MBps
• Maximum Forward Diode Voltage: 1.85 V
• Maximum Reverse Diode Voltage: 5 V (Min)
• Maximum Input Diode Current: 6 mA
• Maximum Power Dissipation: 600 mW
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 1. Effects of Common Mode Pulse Direction on Transient I
CMR with Other Drive Circuits
CMR performance with drive circuits other than that
shown in Figure 13 may be enhanced by following these
guidelines:
1. Use of drive circuits where current is shunted from the
2. Use
Using any one of the drive circuits in Figures 15-17 with
I
W70L AND ACPL-K73L, as long as the PC board layout
practices are followed. Figure 15 shows a circuit which can
be used with any totem-pole-output TTL/LSTTL/HCMOS
logic gate. The buffer PNP transistor allows the circuit to
be used with logic devices which have low current-sinking
capability. It also helps maintain the driving-gate power-
supply current at a constant level to minimize ground
shifting for other devices connected to the input-supply
ground.
Figure 15. TTL interface circuit for the ACPl-W70L families.
13
F
If
dV
positive (>0)
negative (<0) toward LED anode through C
TTL/CMOS
= 6 mA will result in a typical CMR of 10 kV/μs for ACPL-
74L504
CM
LED in the LED “off” state (as shown in Figures 15 and
16). This is beneficial for good CM
recommendation.
GATE)
(ANY
/dt Is:
of
typical
then
I
away from LED anode through C
LP
Flows:
V
DD
I
2N3906
FH
(ANY PNP)
=
530 :
6mA
H
.
LA
1
3
per
LA
ACPL-W70L
datasheet
and
I
away from LED cathode through C
toward LED cathode through C
LED
LN
Flows:
LED
Figure 16. TTL open-collector/open drain gate drive circuit for ACPL-W70L
families.
Figure 17. CMOS gate drive circuit for ACPL-W70L families.
When using an open-collector TTL or open-drain CMOS
logic gate, the circuit in Figure 16 may be used. When
using a CMOS gate to drive the optocoupler, the circuit
shown in Figure 17, where the resistor is recommended to
connect to the anode of the LED, may be used.
OPEN-COLLECTOR
OUTPUT LOGIC
TOTEM-POLE
/OPEN-DRAIN
V
LOGIC GATE)
DD
(OR ANY
74HC04
(OR ANY
GATE)
74HC00
V
DD
LC
LC
If |I
LED I
Is Momentarily:
increased
decreased
530 :
LP
F
| < |I
Current
LN
530 :
|,
If |I
LED I
Is Momentarily:
decreased
increased
1
3
1
3
LP
F
| < |I
ACPL-W70L
ACPL-W70L
Current
LN
|,
LED
LED