MT4VDDT3264AY-40BF1 Micron Technology Inc, MT4VDDT3264AY-40BF1 Datasheet - Page 9

• Manufacturer Part Number: MT4VDDT3264AY-40BF1
• Description: MODULE DDR 256MB 184-UDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3264AY-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 200MHz
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 860mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1342

Idd Specifications
Table 9:
PDF: 09005aef8085081a/Source: 09005aef806e129d
DD4C16_32x64A.fm - Rev. E 11/08 EN
Parameter/Condition
Operating one device bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one device bank active-read-precharge current: Burst = 4;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ, DQS, and DM
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: Burst = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: Burst = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock cycle;
t
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
READs (burst = 4) with auto precharge;
Address and control inputs change only during active READ or WRITE
commands
CK =
RC =
RC =
CK =
CK =
t
t
t
t
t
RAS (MAX);
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK (MIN); Iout = 0mA
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
t
t
CK =
CK =
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
Idd Specifications and Conditions – 128MB (Die Revision K)
Values are for the MT46V16M16 DDR SDRAM only and are computed from values specified in the
256Mb (16 Meg x 16) component data sheet
t
CK =
t
CK =
t
CK (MIN); Iout = 0mA; Address and control inputs
t
CK (MIN); DQ, DM, and DQS inputs changing twice per
t
RC =
t
RC (MIN);
128MB, 256MB (x64, SR) 184-Pin DDR SDRAM UDIMM
t
CK =
t
t
RFC =
RFC = 7.8125µs
t
CK =
t
RC =
9
t
CK (MIN);
t
t
RFC (MIN)
CK (MIN);
t
RC (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
Idd4W
Idd3N
Idd4R
Idd5A
Idd2P
Idd2F
Idd3P
Idd0
Idd1
Idd5
Idd6
Idd7
Electrical Specifications
©2003 Micron Technology, Inc. All rights reserved.
-40B
1160
400
480
200
140
240
720
720
640
16
24
16
1080
-335
360
460
200
120
220
640
640
640
16
24
16
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA