MT4VDDT1664HG-265F3 Micron Technology Inc, MT4VDDT1664HG-265F3 Datasheet - Page 22

• Manufacturer Part Number: MT4VDDT1664HG-265F3
• Description: MODULE SDRAM DDR 128MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT1664HG-265F3

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 266MT/s
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef8086ea3d, source: 09005aef8086ea0b
DD4C8_16_32x64HG.fm - Rev. C 9/04 EN
80
70
60
50
40
30
20
10
35. The voltage levels used are derived from a mini-
36. V
37. V
38.
39.
40. During initialization, V
0
Figure 11: Reduced Output Pull-Down
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
e. The full variation in the ratio of the maximum
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
f. The full variation in the ratio of the nominal
t
IH
IL
DD
RPST), or begins driving (
TT
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
(MIN) = -1.5V for a pulse width
overshoot: V
and V
may be 1.35V maximum during power up,
t
DQSCK (MIN) +
0.5
DD
DD
DD
level and the referenced test load. In
/V
Characteristics
Q must track each other.
DD
3ns and the pulse width can not be
Q are 0V, provided a minimum of
IH
1.0
(MAX) = V
V
t
OUT
RPRE (MAX) condition.
t
RPRE begin point are not
DD
(V)
DD
t
Q, V
t
LZ (MIN) will prevail
RPRE).
1.5
+ 0.3V. Alternatively,
TT
t
DD
DQSCK (MAX) +
, and V
Q + 1.5V for a
IL
undershoot:
2.0
3ns and the
Minimum
REF
must
2.5
22
41. The current Micron part operates below the slow-
42. Random addressing changing and 50 percent of
43. Random addressing changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. I
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
49. The -335 speed grade will operate with
-10
-20
-30
-40
-50
-60
-70
-80
64MB, 128MB, 256MB (x64, SR)
Figure 12: Reduced Output Pull-Up
0
0.0
200-PIN DDR SDRAM SODIMM
42
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic high or logic low.
= 40ns and
frequency.
RFC later.
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2N specifies the DQ, DQS, and DM to be
2
F
of series resistance is used between the V
is “worst case.”
0.5
DD
t
RAS (MAX) = 120,000ns at any slower
Characteristics
DD
2
F
2
, I
F
DD
1.0
except I
V
DD
2
Q - V
N
, and I
©2004 Micron Technology, Inc. All rights reserved.
OUT
(V)
1.5
DD
DD
2
Q
2
Q
specifies the
are similar,
2.0
t
RAS (MIN)
Nominal low
Minimum
DD
2
Q
TT
2.5
is