SI5338-EVB Silicon Laboratories Inc, SI5338-EVB Datasheet - Page 28

• Manufacturer Part Number: SI5338-EVB
• Description: BOARD EVALUATION SI5338
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5338-EVB

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: Si5338
• Primary Attributes: 160 kHz to 700 MHz in LVPECL/LVDS,
• Secondary Attributes: USB Based GUI to Program, I2C/SMBus Compatible Interface, 1.8, 2.5, or 3.3 V
• For Use With/related Products: Si5330/34/38 Family
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1556

Si5338
4.2. Synchronous Frequency Translation
In other cases, it is useful to generate an output
frequency that is synchronous (or phase-locked) to
another clock frequency. The Si5338 is the ideal choice
for generating up to four clocks with different
frequencies with a fixed phase relationship to an input
reference. Because of its highly precise frequency
synthesis, the Si5338 can generate all four output
frequencies with 0 ppm error to the input reference. The
Si5338 is an ideal choice for applications that have
traditionally required multiple stages of frequency
synthesis to achieve complex frequency translations.
Examples are in broadcast video (e.g., 148.5 MHz to
148.351648351648 MHz), WAN/LAN applications (e.g.
155.52 MHz to 156.25 MHz), and Forward Error
Correction (FEC) applications (e.g., 156.25 MHz to
161.1328125 MHz). Using the input reference selectors,
the Si5338 can select from one of four inputs (IN1/IN2,
IN3, IN4, and IN5/IN6). Figure 18 shows the Si5338
configured
Frequencies and multiplication ratios may be entered
into ClockBuilder Desktop using fractional notation to
ensure that the exact scaling ratios can be achieved.
28
F
Figure 18. Si5338 as a Synchronous Clock
in
Generator or Frequency Translator
Si5338
as
P1
P2
a
synchronous
ref
PLL
MS0
MS1
MS2
MS3
clock
R0
R1
R2
R3
generator.
F
F
F
F
0
1
2
3
Rev. 1.0
4.3. Configurable Buffer and Level
Using the output selectors, the synthesis stage can be
entirely bypassed allowing the Si5338 to act as a
configurable clock buffer/divider with level translation
and selectable inputs. Because of its highly selectable
configuration, virtually any combination is possible. The
configurable output drivers allow four differential
outputs, eight single-ended outputs, or a combination of
both. Figure 19 shows the Si5338 configured as a
flexible clock buffer.
4.3.1. Combination Free-Running and Synchronous
Another application of the Si5338 is in generating both
free-running and synchronous clocks in one device.
This is accomplished by configuring the input and
output selectors for the desired split configuration. An
example of such an application is shown in Figure 20.
F
in
XTAL
Synchronous Clock Generator Application
Figure 19. Si5338 as a Configurable Clock
Figure 20. Si5338 In a Free-Running and
Translator
Buffer/Divider with Level Translation
Clock Generator
F
in
S i5 3 3 8
Si5338
Osc
P2
ref
PLL
R 0
R 1
R 2
R 3
MS2
MS3
R0
R1
R2
R3
F
F
F
F
in
in
in
in
*
*
*
*
R 0
R 1
R 2
R 3
1
1
1
1
F
F
F
F
0
1
2
3