CDB5376 Cirrus Logic Inc, CDB5376 Datasheet - Page 10

• Manufacturer Part Number: CDB5376
• Description: EVALUATION BOARD FOR CS5376
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5376

• Main Purpose: Seismic Evaluation System
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS3301A, CS3302A, CS4373A, CS5372A, CS5376A
• Primary Attributes: Quad Digital Filter
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Processor To Be Evaluated: CS330x, CS4373A, CS537x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1778

DIGITAL CHARACTERISTICS (CONT.)
Notes: 20. MCLK is generated by the digital filter. If MCLK is disabled, the device automatically enters a power-
10
Master Clock Input
MCLK Frequency
MCLK Period
MCLK Duty Cycle
MCLK Rise Time
MCLK Fall Time
MCLK Jitter (in-band or aliased in-band)
MCLK Jitter (out-of-band)
Master Sync Input
MSYNC Setup Time to MCLK Falling
MSYNC Period
MSYNC Hold Time after MCLK Falling
MDATA Output
MDATA Output Bit Rate
MDATA Output Bit Period
MDATA Output One’s Density Range
Full-scale Output Code
21. MSYNC is generated by the digital filter and is latched on MCLK falling edge, synchronization instant
22. Decimated, filtered, and offset-corrected 24-bit output word from the digital filter.
down state.
(t
0
) is on the next MCLK rising edge.
Parameter
(Note 9,
(Note 9,
(Note 9,
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
20)
20)
21)
21)
21)
22)
9)
9)
9)
9)
9) MCLK
9)
MCLK
MCLK
MDAT
MDAT
Symbol
t
f
t
t
t
msync
t
mdata
mdata
f
t
t
RISE
FALL
CLK
mclk
mss
msh
OBJ
OD
DC
IBJ
FS
0xA2EBE0
Min
40
20
40
20
14
-
-
-
-
-
-
-
-
CS5371A CS5372A
2.048
1953
Typ
488
122
976
122
512
-
-
-
-
-
-
-
0x5D1420
Max
300
60
50
50
86
1
-
-
-
-
-
-
-
kbits/s
MHz
Unit
DS748F3
ns
ns
ns
ps
ns
ns
ns
ns
ns
%
%