SI5367/68-EVB Silicon Laboratories Inc, SI5367/68-EVB Datasheet - Page 5

• Manufacturer Part Number: SI5367/68-EVB
• Description: BOARD EVAL FOR SI5367/68
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5367/68-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5367, SI5368
• Processor To Be Evaluated: Si5367 and Si5368
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

For a differential external reference, connect the balanced input signals to J1 and J2. For single-ended operation,
connect the input signal to J1 and disconnect J2.
R51 is provided so that a different termination scheme can be used. If R51 is populated, then remove R52 and R24.
5.4. CPLD
This CPLD is required for the MCU to control the Si536x over a flexible 1.8 or 2.5 V V
main functions: it translates the voltage level from 3.3 V (the MCU voltage) to the Si536x voltage (either 1.8 or
2.5 V). The MCU communicates to the CPLD with the SPI signals SS_CPLD_B (slave select), MISO (master in,
slave out), MOSI (master out, slave in) and SCLK. The MCU can talk to CPLD-resident registers that are
connected to pins that control the Si536x's pins, mainly for pin control mode. When the MCU wishes to access a
Si536x register, the SPI signals are passed through the CPLD, while being level translated, to the Si536x. The
CPLD is an EE device that is retains its code that is loaded through the JTAG port (J32). The core of the CPLD
runs at 1.8 V, which is provided by voltage regulator U4. The CPLD also logically connects many of the LEDs to the
appropriate Si536x pins.
Notes:
1. Xtal is 114.285 MHz 3rd overtone.
2. For external reference frequencies and RATE pin settings, see the
3. NC—no connect.
4. NOPOP—do not install this component.
Input 1
Input 2
RATE0
RATE1
C39
C22
R50
R28
+3.3 V
Any-Rate Precision Clock Family Reference Manual
MCU
Figure 3. SPI Mode Serial Data Flow
Table 2. Reference Input Mode
SS_CPLD_B
NOPOP
NOPOP
NOPOP
install
SCLK
MOSI
MISO
Xtal
NC
NC
M
M
3
1
4
Rev. 0.4
38.88 MHz Ext Ref
CPLD
NOPOP
NOPOP
Mode
install
install
J1
J2
—
—
SS_B
SCLK
SDO
SDI
2
Wide Band
NOPOP
NOPOP
install
install
Si5367, Si5368
Si5367/68-EVB
NC
NC
DUT_PWR
H
H
.
DD
. The CPLD provides two
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