MAX19713EVCMODU+ Maxim Integrated Products, MAX19713EVCMODU+ Datasheet - Page 8

• Manufacturer Part Number: MAX19713EVCMODU+
• Description: EVAL MODULE FOR MAX19713
• Manufacturer: Maxim Integrated Products

Specifications of MAX19713EVCMODU+

• Main Purpose: Interface, Analog Front End (AFE)
• Embedded: No
• Utilized Ic / Part: MAX19713
• Primary Attributes: Dual 45MSPS 10-bit Rx ADCs & Tx DACs
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Separate analog, digital, clock, and buffer power planes
minimize noise coupling between analog and digital sig-
nals. Analog ADC inputs and DAC outputs use 100Ω
differential microstrip transmission lines, while 50Ω
microstrip transmission lines are used for all digital out-
puts and the clock input. The trace lengths of the ADC
input and DAC output paths are well matched to mini-
mize layout-dependent input-signal skew.
For optimal performance, the MAX19710–MAX19713
EV kits require separate analog, digital, clock, and
buffer power supplies; however, two separate +3.0V
and +1.8V power supplies are recommended to power
the analog (VDD) and digital (OVDD) portions of the
AFEs, respectively. The clock circuitry (CVDD) is pow-
ered by a +3.0V power supply. The DAC outputs are
buffered by split-supply op amps. Power the positive
rail (VOP) with a +5V supply and the negative rail
(VON) with a -5V supply. A separate +1.8V power sup-
ply (BVCC) can be used to isolate the power source to
the buffer driver (U2). See Table 1 for the proper
jumper configurations for JU3.
If the OVDD current is measured at the OVDD and
OGND pads on the EV kit, a measurement error occurs
due to the extra current flowing into U2. Power U2
through BVCC for a more accurate measurement of the
OVDD current into the AFEs.
An on-board clock-shaping circuit generates a clock
signal from an AC sine-wave signal applied to the
CLOCK SMA connector. The frequency of the signal
should not exceed 45MHz for the MAX19713 (see the
Part Selection Table for the maximum sampling rate of
other devices). The frequency of the sinusoidal input
signal determines the sampling frequency (f
AFEs. A differential line receiver (U3) processes the
input signal to generate the CMOS clock signal. The
signal’s duty cycle can be adjusted with potentiometer
R63. A clock signal with a 50% duty cycle (recom-
mended) is achieved by adjusting R63 until 1.32V is
produced across test points TP4 and TP5 when the
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
Table 1. U2 Power Source (JU3)
* Default configuration.
8
POSITION
_______________________________________________________________________________________
SHUNT
1-2*
2-3
U2 is powered through OVDD.
U2 is powered through BVCC.
(Note: BVCC must equal OVDD.)
DESCRIPTION
Power Supplies
CLK
Clock
) of the
clock voltage supply (CVDD) is set to +3.0V. The clock
signal is available at J2-3 (CLKOUT), which can be used
to synchronize the output signal to the logic analyzer.
Measure the clock signal with an oscilloscope at TP3.
Although the MAX19710–MAX19713 AFEs accept differ-
ential analog input signals, the EV kits only require a
single-ended analog input signal provided by the user.
Connect the single-ended sources to the IA SMA con-
nector (I channel) and QA SMA connector (Q channel).
Insertion losses due to series-connected bandpass
filters and the interconnecting cables decrease the
amount of power seen at the EV kit input. Account for
these losses when setting the signal generator
amplitude. On-board transformers (T1, T2) convert the
single-ended analog input signals and generate differ-
ential analog signals at the ADC’s differential input pins.
The AFEs also accept single-ended input signals. See
the Configuring for Single-Ended ADC Operation sec-
tion for details on how to modify the EV kits to support
this mode of operation.
The MAX19710–MAX19713 can be configured to
accept AC-coupled, single-ended signals presented at
the input. Configure the EV kit to support this mode of
operation by completing the following steps:
Configure the EV kit for DC-coupled, single-ended sig-
nals by removing capacitors C1 and C2, removing resis-
tors R9 and R10, and installing 0Ω resistors at locations
R5 and R6.
By default, on-board ultra-low-distortion op amps (U4 and
U5) buffer the DAC outputs on the MAX19710–
MAX19713 EV kits. The op amps convert the differential
signal from the AFEs to a single-ended 50Ω signal.
Measure the buffered output signals at the QD SMA con-
nector (Q channel) and the ID SMA connector
(I channel).
Measure the differential output of the AFEs at the
IDN/IDP and QDN/QDP pads. Full-scale output, offset
voltage, and common-mode voltage functions are con-
trolled through the EV kit software.
1) Cut open the traces at locations R11–R14.
2) Install 0Ω resistors at locations R7–R10, R15,
and R16.
3) Install 2kΩ ±1% resistors at locations R21–R24.
4) Connect the single-ended sources to the IAP
connector (I channel) and/or to the QAP SMA
connector (Q channel).
Configuring for Single-Ended ADC Operation
Tx DAC Outputs
Rx ADC Inputs