EVAL-AD7623CBZ Analog Devices Inc, EVAL-AD7623CBZ Datasheet - Page 15

• Manufacturer Part Number: EVAL-AD7623CBZ
• Description: BOARD EVALUATION FOR AD7623
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7623CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1.33M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 50mW @ 1.33MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7623
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7623 is a very fast, low power, single-supply, precise,
16-bit analog-to-digital converter (ADC) using successive
approximation architecture. The AD7623 is capable of
converting 1,330,000 samples per second (1.33 MSPS).
The AD7623 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7623 can be operated from a single 2.5 V supply and
be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. It
is housed in 48-lead LQFP or tiny LFCSP packages that
combine space savings with flexibility, allowing the AD7623
to be configured as either a serial or parallel interface. The
AD7623 is pin-to-pin-compatible with, and a speed upgrade
of, the AD7677.
CONVERTER OPERATION
The AD7623 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
REFGND
REF
IN+
IN–
32,768C 16,384C
32,768C 16,384C
MSB
MSB
4C
4C
Figure 21. ADC Simplified Schematic
2C
2C
Rev. 0 | Page 15 of 28
C
C
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN− inputs. A conversion
phase is initiated once the acquisition phase is complete and the
CNVST input goes low. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
inputs (IN+ and IN−) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the
comparator input varies by binary weighted voltage steps
(V
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.
The AD7623 automatically powers down circuits after
conversion, making the AD7623 ideal for battery-powered
applications.
C
C
REF
LSB
LSB
AGND
/2, V
AGND
SW–
SW+
REF
COMP
/4 through V
SWITCHES
CONTROL
CONTROL
CNVST
LOGIC
REF
/65536). The control logic toggles
OUTPUT
CODE
BUSY
AD7623