ADC102S101EVAL National Semiconductor, ADC102S101EVAL Datasheet - Page 16

• Manufacturer Part Number: ADC102S101EVAL
• Description: BOARD EVALUATION FOR ADC102S101
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC102S101EVAL

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 11.4mW @ 1MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC102S101
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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During each conversion, data is clocked into the ADC at DIN
on the first 8 rising edges of SCLK after the fall of CS. For
each conversion, it is necessary to clock in the data indicating
the input that is selected for the conversion after the current
one. See Tables 1, 2 and
If CS and SCLK go low within the times defined by t
t
DIN may be one clock cycle later than expected. It is, there-
CLH
, the rising edge of SCLK that begins clocking data in at
Bit 7 (MSB)
DONTC
Bit #:
7 - 6, 2 - 0
3
4
5
ADD2
Symbol:
Table
DONTC
x
x
x
Bit 6
DONTC
ADD0
ADD1
ADD2
3.
ADD1
0
0
1
TABLE 2. Control Register Bit Descriptions
Description
Don't care. The value of these bits do not affect the device.
These bits determine which input channel will be sampled and converted in the
next track/hold cycle. The mapping between codes and channels is shown in
Table
ADD2
Bit 5
TABLE 3. Input Channel Selection
TABLE 1. Control Register Bits
3.
ADD0
0
1
x
CSU
ADD1
and
Bit 4
Not allowed. The output signal at the D
16
is indeterminate if ADD1 is high.
fore, best to strictly observe the minimum t
given in the Timing Specifications.
There are no power-up delays or dummy conversions re-
quired with the ADC102S101. The ADC is able to sample and
convert an input to full conversion immediately following pow-
er up. The first conversion result after power-up will be that of
IN1.
ADD0
Bit 3
Input Channel
IN1 (Default)
IN2
DONTC
Bit 2
OUT
DONTC
Bit 1
pin
CSU
and t
DONTC
Bit 0
CLH
times