ADC122S101EVAL National Semiconductor, ADC122S101EVAL Datasheet - Page 15

• Manufacturer Part Number: ADC122S101EVAL
• Description: BOARD EVALUATION FOR ADC122S101
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC122S101EVAL

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 13.1mW @ 1MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC122S101
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Applications Information
1.0 ADC122S101 OPERATION
The ADC122S101 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution dig-
ital-to-analog converter. Simplified schematics of the AD-
C122S101 in both track and hold modes are shown in
Figures 1, 2, respectively. In
track mode: switch SW1 connects the sampling capacitor to
one of two analog input channels through the multiplexer, and
SW2 balances the comparator inputs. The ADC122S101 is in
this state for the first three SCLK cycles after CS is brought
low.
Figure 2
connects the sampling capacitor to ground, maintaining the
2.0 USING THE ADC122S101
An ADC122S101 timing diagram and a serial interface timing
diagram for the ADC122S101 are shown in the Timing Dia-
grams section. CS is chip select, which initiates conversions
and frames the serial data transfers. SCLK (serial clock) con-
trols both the conversion process and the timing of serial data.
DOUT is the serial data output pin, where a conversion result
is sent as a serial data stream, MSB first. Data to be written
to the ADC122S101's Control Register is placed at DIN, the
serial data input pin. New data is written to DIN with each
conversion.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. Each frame must contain an integer
multiple of 16 rising SCLK edges. The ADC output data
(DOUT) is in a high impedance state when CS is high and is
active when CS is low. Thus, CS acts as an output enable.
shows the ADC122S101 in hold mode: switch SW1
Figure
1, the ADC122S101 is in
FIGURE 1. ADC122S101 in Track Mode
FIGURE 2. ADC122S101 in Hold Mode
15
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add fixed amounts of charge to the sampling capacitor
until the comparator is balanced. When the comparator is
balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC122S101
is in this state for the fourth through sixteenth SCLK cycles
after CS is brought low.
The time when CS is low is considered a serial frame. Each
of these frames should contain an integer multiple of 16 SCLK
cycles, during which time a conversion is performed and
clocked out at the DOUT pin and data is clocked into the DIN
pin to indicate the multiplexer address for the next conversion.
Additionally, the device goes into a power down state when
CS is high and also between continuous conversion cycles.
During the first 3 cycles of SCLK, the ADC is in the track
mode, acquiring the input voltage. For the next 13 SCLK cy-
cles the conversion is accomplished and the data is clocked
out, MSB first, starting on the 5th clock. If there are more than
one conversion in a frame, the ADC will re-enter the track
mode on the falling edge of SCLK after the N*16th rising edge
of SCLK, and re-enter the hold/convert mode on the N*16+4th
falling edge of SCLK, where "N" is an integer.
When CS is brought high, SCLK is internally gated off. If SCLK
is stopped in the low state while CS is high, the subsequent
fall of CS will generate a falling edge of the internal version of
SCLK, putting the ADC into the track mode. This is seen by
the ADC as the first falling edge of SCLK. If SCLK is stopped
with SCLK high, the ADC enters the track mode on the first
falling edge of SCLK after the falling edge of CS.
20125209
20125210
www.national.com