ADC14C105EB/NOPB National Semiconductor, ADC14C105EB/NOPB Datasheet - Page 3

• Manufacturer Part Number: ADC14C105EB/NOPB
• Description: BOARD EVAL 14-BIT ADC14C105
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14C105EB/NOPB

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 400mW @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14C105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14C105EB

ANALOG I/O
DIGITAL I/O
Pin Descriptions and Equivalent Circuits
Pin No.
32
31
12
11
30
5
6
2
1
OF/DCS
Symbol
V
V
V
CLK
V
V
V
PD
CMO
REF
IN
IN
RN
RP
+
-
Equivalent Circuit
3
Differential analog input pins. The differential full-scale input signal
level is 2V
mode voltage, V
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close
to the pin to minimize stray inductance. A 0.1 µF capacitor should
be placed between V
and a 1 µF capacitor should be placed in parallel.
V
for use as a temperature stable 1.5V reference.
It is recommended to use V
voltage, V
Reference Voltage. This device provides an internally developed
1.2V reference. When using the internal reference, V
decoupled to AGND with a 0.1 µF and a 1 µF low equivalent series
inductance (ESL) capacitor .
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current.
This is a four-state pin controlling the input clock mode and output
data format.
OF/DCS = V
cycle stabilization applied to the input clock
OF/DCS = AGND, output data format is offset binary, without duty
cycle stabilization applied to the input clock.
OF/DCS = (2/3)*V
stabilization applied to the input clock
OF/DCS = (1/3)*V
stabilization applied to the input clock.
The clock input pin.
The analog input is sampled on the rising edge of the clock input.
This is a two-state input controlling Power Down.
PD = V
PD = AGND, Normal operation.
RP
and V
A
, Power Down is enabled and power dissipation is reduced.
CM
P-P
RN
, for the differential analog inputs, V
A
should not be loaded. V
with each input pin signal centered on a common
, output data format is 2's complement without duty
CM
A
A
.
, output data is 2's complement with duty cycle
, output data is offset binary with duty cycle
RP
and V
Description
CMO
RN
to provide the common mode
as close to the pins as possible,
CMO
may be loaded to 1mA
IN
+ and V
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REF
should be
IN
−.