ADC12C105EB/NOPB National Semiconductor, ADC12C105EB/NOPB Datasheet - Page 20

• Manufacturer Part Number: ADC12C105EB/NOPB
• Description: BOARD EVALUATION FOR ADC12C105
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC12C105EB/NOPB

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 105M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 400mW @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC12C105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC12C105EB

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always be bypassed to ground with a 0.1 µF capacitor close
to the reference input pin.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects of
noise currents in the ground path.
The Reference Bypass Pins (V
available for bypass purposes. These pins should each be
bypassed to AGND with a low ESL (equivalent series induc-
tance) 1 µF capacitor placed very close to the pin to minimize
stray inductance. A 0.1 µF capacitor should be placed be-
tween V
µF capacitor should be placed in parallel. This configuration
is shown in Figure 7. It is necessary to avoid reference oscil-
lation, which could result in reduced SFDR and/or SNR.
V
1.5V reference. The remaining pins should not be loaded.
Smaller capacitor values than those specified will allow faster
recovery from the power down mode, but may result in de-
graded noise performance. Loading any of these pins, other
than V
The nominal voltages for the reference bypass pins are as
follows:
2.3 OF/DCS Pin
Duty cycle stabilization and output data format are selectable
using this quad state function pin. When enabled, duty cycle
stabilization can compensate for clock inputs with duty cycles
ranging from 30% to 70% and generate a stable internal clock,
improving the performance of the part. With OF/DCS = V
output data format is 2's complement and duty cycle stabi-
lization is not used. With OF/DCS = AGND the output data
format is offset binary and duty cycle stabilization is not used.
With OF/DCS = (2/3)*V
plement and duty cycle stabilization is applied to the clock. If
OF/DCS is (1/3)*V
duty cycle stabilization is applied to the clock. While the sense
of this pin may be changed "on the fly," doing this is not rec-
ommended as the output data could be erroneous for a few
clock cycles after this change is made.
3.0 DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, and PD.
3.1 Clock Input
The CLK controls the timing of the sampling process. To
achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the
range indicated in the Electrical Table. The clock input signal
should also have a short transition region. This can be
achieved by passing a low-jitter sinusoidal clock source
through a high speed buffer gate. The trace carrying the clock
signal should be as short as possible and should not cross
any other signal line, analog or digital, not even at 90°.
The clock signal also drives an internal state machine. If the
clock is interrupted, or its frequency is too low, the charge on
the internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the minimum sample rate.
The clock line should be terminated at its source in the char-
acteristic impedance of that line. Take care to maintain a
CMO
V
V
V
CMO
RP
RN
may be loaded to 1mA for use as a temperature stable
CMO
= 2.0 V
= 1.0 V
RP
= 1.5 V
may result in performance degradation.
and V
RN
A
the output data format is offset binary and
as close to the pins as possible, and a 1
A
the output data format is 2's com-
RP
, V
CMO
, and V
RN
) are made
A
the
20
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on set-
ting characteristic impedance.
It is highly desirable that the the source driving the ADC clock
pins only drive that pin. However, if that source is used to drive
other devices, then each driven pin should be AC terminated
with a series RC to ground, such that the resistor value is
equal to the characteristic impedance of the clock line and the
capacitor value is
where t
"L" is the line length and Z
of the clock line. This termination should be as close as pos-
sible to the ADC clock pin but beyond it as seen from the clock
source. Typical t
board material. The units of "L" and t
(inches or centimeters).
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty cycle
is difficult, the ADC12C105 has a Duty Cycle Stabilizer. It is
designed to maintain performance over a clock duty cycle
range of 30% to 70%.
3.2 Power-Down (PD)
The PD pin, when high, holds the ADC12C105 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 5 mW if
the clock is stopped when PD is high. The output data pins
are undefined and the data in the pipeline is corrupted while
in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on pins 1, 2, and 32 and is about 3
ms with the recommended components on the V
V
charge in the Power Down mode and must be recharged by
on-chip circuitry before conversions can be accurate. Smaller
capacitor values allow slightly faster recovery from the power
down mode, but can result in a reduction in SNR, SINAD and
ENOB performance.
4.0 DIGITAL OUTPUTS
Digital outputs consist of the CMOS signals D0-D11, and
DRDY.
The ADC12C105 has 13 CMOS compatible data output pins
corresponding to the converted input value and a data ready
(DRDY) signal that should be used to capture the output data.
Valid data is present at these outputs while the PD pin is low.
Data should be captured and latched with the rising edge of
the DRDY signal.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. The result could
be an apparent reduction in dynamic performance.
RN
reference bypass pins. These capacitors loose their
PD
is the signal propagation rate down the clock line,
DR
and DRGND. These large charging current
PD
is about 150 ps/inch (60 ps/cm) on FR-4
O
is the characteristic impedance
PD
should be the same
RP
, V
CMO
and