HI5762EVAL2 Intersil, HI5762EVAL2 Datasheet

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HI5762EVAL2

Manufacturer Part Number
HI5762EVAL2
Description
EVALUATION MOD FOR HI5762 AMP
Manufacturer
Intersil
Datasheets

Specifications of HI5762EVAL2

Number Of Adc's
2
Number Of Bits
10
Sampling Rate (per Second)
60M
Data Interface
Parallel
Inputs Per Adc
2 Differential
Input Range
1 Vpp
Power (typ) @ Conditions
650mW @ 60MSPS
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
HI5762
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Dual 10-Bit, 60MSPS A/D Converter with
Internal Voltage Reference
The HI5762 is a monolithic, dual 10-bit, 60MSPS
analog-to-digital converter fabricated in an advanced CMOS
process. It is designed for high speed applications where
integration, bandwidth and accuracy are essential. Built by
combining two cores of the HI5767 single channel 10-bit
60MSPS analog-to-digital converter, the HI5762 reaches a
new level of multi-channel integration. The fully pipeline
architecture and an innovative input stage enable the
HI5762 to accept a variety of input configurations, single-
ended or fully differential. Only one external clock is
necessary to drive both converters and an internal band-gap
voltage reference is provided. This allows the system
designer to realize an increased level of system integration
resulting in decreased cost and power dissipation.
The HI5762 has excellent dynamic performance while
consuming only 650mW of power at 60MSPS. The A/D only
requires a single +5V power supply and encode clock. Data
output latches are provided which present valid data to the
output bus with a latency of 6 clock cycles.
For those customers needing dual channel 8-bit resolution,
please refer to the HI5662. For single channel 10-bit
applications, please refer to the HI5767.
Ordering Information
NOTES:
HI5762/6IN
HI5762/6INZ
(Notes 1, 2)
HI5762EVAL2
1. These Intersil Pb-free plastic packaged products employ special Pb-
2. For Moisture Sensitivity Level (MSL), please see device
NUMBER
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
information page for HI5762. For more information on MSL
please see techbrief TB363.
PART
HI5762/6IN
HI5762 /6INZ
MARKING
PART
®
-40 to +85 44 Ld MQFP Q44.10x10
-40 to +85 44 Ld MQFP
RANGE
1
TEMP.
(°C)
25
Data Sheet
(Pb-free)
Evaluation Platform
PACKAGE
Q44.10x10
1-888-INTERSIL or 1-888-468-3774
DWG. #
PKG.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 60MSPS
• 8.8 Bits at f
• Low Power at 60MSPS . . . . . . . . . . . . . . . . . . . . 650mW
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
• Excellent Channel-to-Channel Isolation . . . . . . . . . .>75dB
• On-Chip Sample and Hold Amplifiers
• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V
• Fully Differential or Single-Ended Analog Inputs
• Single Supply Voltage Operation . . . . . . . . . . . . . . . . .+5V
• TTL/CMOS Compatible Sampling Clock Input
• CMOS Compatible Digital Outputs. . . . . . . . . . . 3.0V/5.0V
• Offset Binary Digital Data Output Format
• Dual 10-Bit A/D Converters on a Monolithic Chip
Applications
• Wireless Local Loop
• PSK and QAM I&Q Demodulators
• Medical Imaging
• High Speed Data Acquisition
January 22, 2010
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
IN
Copyright Intersil Americas Inc. 1999, 2010. All Rights Reserved
= 10MHz
HI5762
FN4318.3

Related parts for HI5762EVAL2

HI5762EVAL2 Summary of contents

Page 1

... HI5762/6IN - MQFP Q44.10x10 HI5762/6INZ HI5762 /6INZ - MQFP (Notes 1, 2) HI5762EVAL2 25 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

Page 2

Pinout A GND GND 2 HI5762 HI5762 (44 LD MQFP) TOP VIEW CC2 3 ID9 4 ID8 5 ID7 6 ID6 7 ID5 8 ...

Page 3

Functional Block Diagram I I S/H FLASH + ∑ FLASH + ∑ FLASH V REFOUT REFERENCE V REFIN 3 HI5762 BIAS STAGE 1 2-BIT 2-BIT DAC STAGE 8 2-BIT 2-BIT DAC STAGE ...

Page 4

Typical Application Schematic 0.1µF +5V + 10µF 0.1µF BNC 4 HI5762 HI5762 (LSB) ID0 (14) (42 ID1 (13) (44 ID2 (12) (43) I ...

Page 5

Pin Descriptions PIN NO. NAME DESCRIPTION 1 A Analog Ground GND 2 AV Analog Supply (+5.0V) CC2 3 ID9 I-Channel, Data Bit 9 Output (MSB) 4 ID8 I-Channel, Data Bit 8 Output 5 ID7 I-Channel, Data Bit 7 Output 6 ...

Page 6

... HI5762 Thermal Information Thermal Resistance (Typical, Note MQFP Package . . . . . . . . . . . . . . . . . . . . . . . CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C CC Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = DV = +5.0V +3.0V; V CC1,2 CC3 RIN = +25°C; Differential Analog Input; Unless Otherwise Specified A ...

Page 7

Electrical Specifications AV CC1 10pF PARAMETER Analog Input Capacitance IN+ IN- Analog Input Bias Current Differential Analog Input Bias Current ...

Page 8

Electrical Specifications AV CC1 10pF PARAMETER Digital Supply Voltage, DV and DV CC1 CC2 Digital Output Supply Voltage, DV CC3 Supply Current Power Dissipation Offset Error Sensitivity, ΔV OS Gain Error Sensitivity, ΔFSE NOTES: ...

Page 9

Timing Waveforms (Continued) ANALOG INPUT CLOCK 1.5V INPUT DATA OUTPUT Typical Performance Curves 10M INPUT FREQUENCY (Hz) FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) AND SINAD vs INPUT FREQUENCY 90 85 -2HD 80 -3HD 75 ...

Page 10

Typical Performance Curves DUTY CYCLE (%, t FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs SAMPLE CLOCK DUTY CYCLE 9.0 Q CHANNEL I CHANNEL 8.5 8.0 7.5 7.0 ...

Page 11

Typical Performance Curves 140 I CC 120 100 CC1 20 DI CC3 0 -40 - TEMPERATURE (°C) FIGURE 13. SUPPLY CURRENT vs TEMPERATURE DIFFERENTIAL INPUT CODE CENTER DESCRIPTION 1 +Full Scale (+FS) ...

Page 12

As illustrated in the “Functional Block Diagram” on page 3 and the timing diagram in Figure 1 on page 8, eight identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the S/H ...

Page 13

... If the part is powered off a single supply then the analog supply can be isolated by a ferrite bead from the digital supply. Refer to the application note “Using Intersil High-Speed A/D Converters” (AN9214) for additional considerations when using high-speed converters. V ...

Page 14

Static Performance Definitions Offset Error ( The midscale code transition should occur at a level above half-scale. Offset is defined as the deviation of the actual code transition from this point. Full-Scale Error (FSE) The last code transition ...

Page 15

I/Q Channel Crosstalk I/Q Channel Crosstalk is a measure of the amount of channel separation or isolation between the two A/D converter cores contained within the dual converter package. The measurement consists of stimulating one channel of the converter with ...

Page 16

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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