MAX1247EVKIT Maxim Integrated Products, MAX1247EVKIT Datasheet - Page 10

• Manufacturer Part Number: MAX1247EVKIT
• Description: EVALUATION KIT FOR MAX1247
• Manufacturer: Maxim Integrated Products

Specifications of MAX1247EVKIT

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: Serial
• Inputs Per Adc: 4 Single or 2 Differential
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 9mW @ 133kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1247
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The MAX1246/MAX1247 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX1246/
MAX1247.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH3, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from two
pairs: CH0/CH1 and CH2/CH3. Configure the channels
with Tables 2 and 3. Please note that the codes for
CH0–CH3 in the MAX1246/MAX1247 correspond to the
codes for CH2–CH5 in the eight-channel (MAX146/
MAX147) versions.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at IN+
is sampled. The return side (IN-) must remain stable within
±0.5LSB (±0.1LSB for best results) with respect to AGND
during a conversion. To accomplish this, connect a 0.1µF
capacitor from IN- (the selected analog input) to AGND.
During the acquisition interval, the channel selected
as the positive input (IN+) charges capacitor C
The acquisition interval spans three SCLK cycles and
ends on the falling SCLK edge after the last bit of the
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
Figure 3. Block Diagram
10
_______________Detailed Description
______________________________________________________________________________________
REFADJ
SHDN
SCLK
COM
CH0
CH1
CH2
CH3
VREF
DIN
CS
15
16
14
9
8
7
2
3
4
5
6
*A ≈ 2.00 (MAX1247)
REGISTER
ANALOG
INPUT
SHIFT
INPUT
MUX
REFERENCE
(MAX1246)
+1.21V
Pseudo-Differential Input
CONTROL
LOGIC
T/H
20kΩ
A
+2.500V
≈ 2.06*
IN
CLOCK
12-BIT
CLOCK
ADC
SAR
REF
INT
OUT
MAX1246
MAX1247
REGISTER
OUTPUT
SHIFT
1
11
10
12
13
DOUT
SSTRB
HOLD
V
DGND
AGND
DD
.
input control word has been entered. At the end of the
acquisition interval, the T/H switch opens, retaining
charge on C
The conversion interval begins with the input multiplexer
switching C
negative input (IN-). In single-ended mode, IN- is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0V
within the limits of 12-bit resolution. This action is equiv-
alent to transferring a 16pF x [(V
from C
which in turn forms a digital representation of the analog
input signal.
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of
conversion, the positive input connects back to IN+,
and C
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
Figure 4. Equivalent Input Circuit
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
COM
CH0
CH1
CH2
CH3
HOLD
HOLD
VREF
charges to the input signal.
INPUT
HOLD
MUX
HOLD
to the binary-weighted capacitive DAC,
|
IN+ - IN-
12-BIT CAPACITIVE DAC
C
CH0/CH1 AND CH2/CH3.
SWITCH
–
as a sample of the signal at IN+.
from the positive input (IN+) to the
C
16pF
HOLD
TRACK
SWITCH
+
|
T/H
is sampled. At the end of the
R
9kΩ
IN
HOLD
ZERO
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
IN
+
COMPARATOR
) - (V
Track/Hold
IN
-)] charge