MAX1280EVC16 Maxim Integrated Products, MAX1280EVC16 Datasheet - Page 15

• Manufacturer Part Number: MAX1280EVC16
• Description: EVAL KIT FOR MAX1280
• Manufacturer: Maxim Integrated Products

Specifications of MAX1280EVC16

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 400k
• Data Interface: Serial
• Inputs Per Adc: 8 Single Ended
• Input Range: ±VREF/2
• Power (typ) @ Conditions: 13.75mW @ 400kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1280
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The external serial clock not only shifts data in and out,
but also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the next
12 SCLK falling edges (Figure 6). SSTRB and DOUT go
into a high-impedance state when CS goes high; after
the next CS rising edge, SSTRB outputs a logic low.
Figure 7 shows the detailed serial-interface timing.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on SCLK’s falling edge after the eighth bit of
the control byte (the PD0 bit) is clocked into DIN. The
start bit is defined as follows:
Once a start bit has been recognized, the current con-
version may only be terminated by pulling SHDN low.
Figure 7. Detailed Serial-Interface Timing
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V
are applied.
The first high bit clocked into DIN after bit 6 of a con-
version in progress is clocked onto the DOUT pin.
SSTRB
DOUT
SCLK
DIN
CS
______________________________________________________________________________________
t
t
CSS
t
DOE
t
STE
CSO
OR
Serial 12-Bit ADCs with Internal Reference
t
DS
t
DH
t
CL
Data Framing
DD1
t
CH
Serial Clock
and V
DD2
The fastest the MAX1280/MAX1281 can run with CS
held low between conversions is 16 clocks per conver-
sion. Figure 8 shows the serial-interface timing neces-
sary to perform a conversion every 16 SCLK cycles. If
CS is tied low and SCLK is continuous, guarantee a
start bit by first clocking in 16 zeros.
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1280/MAX1281 in normal operating mode, ready to
convert with SSTRB = low. The MAX1280/MAX1281
require 10µs to reset after the power supplies stabilize;
no conversions should be initiated during this time. If
CS is low, the first logic 1 on DIN is interpreted as a
start bit. Until a conversion takes place, DOUT shifts out
zeros. Additionally, wait for the reference to stabilize
when using the internal reference.
You can save power by placing the converter in one of
the two low-current operating modes or in full power-
down between conversions. Select the power mode
through bit 1 and bit 0 of the DIN control byte (Tables 1
and 4), or force the converter into hardware shutdown
by driving SHDN to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
t
CP
t
t
DOH
DOV
t
STH
t
STV
Applications Information
t
CSH
t
CSW
Power-On Reset
t
t
t
DOD
CS1
STD
Power Modes
15