CDB4365 Cirrus Logic Inc, CDB4365 Datasheet - Page 27

• Manufacturer Part Number: CDB4365
• Description: EVALUATION BOARD FOR CS4365
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4365

• Number Of Dac's: 6
• Number Of Bits: 24
• Outputs And Type: 6, Differential
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4365
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4365
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1779

DS670F2
4.9
4.9.1
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4365 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the rec-
ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4365 should be connect-
ed to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
(64Fs)
BCKA
DSD Normal Mode
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same
supply, but a decoupling capacitor should still be placed on each supply pin.
Notes: All decoupling capacitors should be referenced to ground.
The CDB4365 evaluation board demonstrates the optimum layout and power supply arrangements.
DSD_SCLK
Not Used
Not Used
DSDAx,
DSDBx
Figure 18. DSD Phase Modulation Mode Diagram
D0
D0
D1
D1
D1
D2
D2
DSDAx,
DSD_SCLK
DSD_SCLK
DSDBx
Not Used
Modulation Mode
DSD Phase
CS4365
(64Fs)
BCKD
(128Fs)
BCKA
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