EVAL-AD5429EB Analog Devices Inc, EVAL-AD5429EB Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD5429EB
• Description: BOARD EVAL FOR AD5429
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5429EB

• Number Of Dac's: 2
• Number Of Bits: 8
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 2.47M
• Data Interface: Serial
• Settling Time: 30ns
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: AD5429
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EVAL-AD5429/AD5439/AD5449EB
Table 1. Control Functions
Control Function
Load and Update DAC A
Initiate Readback on DAC A
Load Input Register of DAC A
Load and Update DAC B
Initiate Readback on DAC B
Load Input Register of DAC B
Update Both DACs
Load Input Registers of Both DACs
Clear Both Outputs to Zero Scale
Clear Both Outputs to Midscale
Table 2. Control Register
Control Register
SDO Configuration
Daisy-Chain Mode
Hardware Clear
Active SCLK Edge
Description
Loads the DAC A register with the entered data-word and updates the DAC A output , irrespective
of the state of LDAC .
Reads the contents of the DAC A input register and displays the value on-screen.
Loads the DAC A register with the entered data-word. The DAC A output is updated only if LDAC is
low.
Loads the DAC B register with entered data-word and updates the DAC B output, irrespective of the
state of LDAC .
Reads the contents of the DAC B input register and displays the value on-screen.
Loads DAC B register with entered data-word. The DAC B output is updated only if LDAC is low.
Updates both DAC outputs with the entered data-word, irrespective of the state of LDAC .
Loads the input registers of both DACs with the entered data-word. Both outputs are updated only
if LDAC is low.
Loads both DACs and updates their outputs with zero-scale code, irrespective of the state of LDAC .
Loads both DACs and updates their outputs with midscale code, irrespective of the state of LDAC .
Description
The SDO bits enable you to control the SDO output driver strength, disable the SDO output, or
configure it as as an open-drain driver. The strength of the SDO driver affects timing. A stronger
SDO output driver allows a faster clock cycle to be used.
Enables or disables daisy-chain functionality.
Sets the value to which the outputs are cleared on the falling edge of the CLR signal. The value can
be either zero scale or midscale.
Selects the edge of SCLK on which data is clocked into the input register. Data is clocked out from
SDO on the opposite edge.
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