EVAL-AD5372EBZ Analog Devices Inc, EVAL-AD5372EBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD5372EBZ
• Description: BOARD EVAL FOR AD5372
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5372EBZ

• Number Of Dac's: 32
• Number Of Bits: 16
• Outputs And Type: 32, Single Ended
• Sampling Rate (per Second): 540k
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
POWER REQUIREMENTS
1
2
3
AC CHARACTERISTICS
DV
offset (C), and DAC offset registers at default values; all specifications T
Table 3.
Parameter
DYNAMIC PERFORMANCE
1
Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
Guaranteed by design and characterization; not production tested.
θ
Guaranteed by design and characterization; not production tested.
JA
DV
V
V
Power Supply Sensitivity
DI
I
I
Power-Down Mode
Power Dissipation (Unloaded)
Junction Temperature
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 10 kHz
DD
SS
CC
represents the package thermal impedance.
DD
SS
CC
∆Full Scale/∆V
∆Full Scale/∆V
∆Full Scale/∆DV
DI
I
I
CC
DD
SS
= 2.5 V; V
CC
DD
= 15 V; V
DD
SS
CC
3
1
2
SS
= −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; C
AD5372
B Version
2.5/5.5
9/16.5
−16.5/−4.5
−75
−75
−90
2
16
18
−16
−18
5
35
−35
250
130
B Version
20
30
1
5
10
100
10
0.2
0.02
250
1
AD5373
B Version
2.5/5.5
9/16.5
−16.5/−4.5
−75
−75
−90
2
16
18
−16
−18
5
35
−35
250
130
Rev. B | Page 5 of 24
Unit
μs typ
μs max
V/μs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV/√Hz typ
1
MIN
Unit
V min/V max
V min/V max
V min/V max
dB typ
dB typ
dB typ
mA max
mA max
mA max
mA max
mA max
μA typ
μA typ
μA typ
mW typ
°C max
to T
Test Conditions/Comments
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s
VREF0, VREF1 = 2 V p-p, 1 kHz
Effect of input bus activity on DAC output under test
VREF0 = VREF1 = 0 V
MAX
, unless otherwise noted.
Test Conditions/Comments
DV
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
Bit 0 in the control register is 1
V
T
J
SS
= T
CC
= −8 V, V
= 5.5 V, V
A
+ P
TOTAL
L
DD
= 200 pF; R
IH
= 9.5 V, DV
× θ
= DV
JA
CC
AD5372/AD5373
, V
IL
L
CC
= 10 kΩ; gain (M),
= GND
= 2.5 V
2