EVAL-AD5373EBZ Analog Devices Inc, EVAL-AD5373EBZ Datasheet - Page 10

• Manufacturer Part Number: EVAL-AD5373EBZ
• Description: BOARD EVAL FOR AD5373
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5373EBZ

• Number Of Dac's: 32
• Number Of Bits: 14
• Outputs And Type: 32, Single Ended
• Sampling Rate (per Second): 540k
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5373
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5372/AD5373
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
42 to 45, 47 to 50, 21
to 24, 26 to 33, 37 to
40, 60 to 62, 3, 5 to 8
4
9 to 15, 19, 20
16, 35
17, 36
18
25
34
41
46
51, 58
52, 57
53
54
55
56
59
63
64
Mnemonic
RESET
BUSY
VOUT0 to
VOUT31
SIGGND3
NC
V
V
VREF1
SIGGND1
SIGGND2
VREF0
SIGGND0
DGND
DV
SYNC
SCLK
SDI
SDO
AGND
LDAC
CLR
DD
SS
CC
SIGGND3
NC = NO CONNECT
VOUT27
VOUT28
VOUT29
VOUT30
VOUT31
RESET
BUSY
Description
Digital Reset Input.
Digital Input/Open-Drain Output. BUSY is open drain when an output. See the BUSY and LDAC Functions
section for more information.
DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output is capable of
driving an output load of 10 kΩ to ground. Typical output impedance of these amplifiers is 0.5 Ω.
Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
No Connect.
Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These pins should be decoupled with
0.1 μF ceramic capacitors and 10 μF capacitors.
Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins should be decoupled
with 0.1 μF ceramic capacitors and 10 μF capacitors.
Reference Input for DAC 8 to DAC 31. This reference voltage is referred to AGND.
Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
Ground for All Digital Circuitry. The DGND pins should be connected to the DGND plane.
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
Active Low Input. This is the frame synchronization signal for the serial interface.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at
clock speeds up to 50 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising
edge of SCLK and is valid on the falling edge of SCLK.
Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane.
Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more information.
Asynchronous Clear Input (Level Sensitive, Active Low). See the
V
NC
NC
NC
NC
NC
NC
NC
DD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
INDICATOR
Figure 7. Pin Configuration
AD5372/AD5373
Rev. B | Page 10 of 24
(Not to Scale)
TOP VIEW
42
41
40
48
47
46
45
44
43
39
38
37
36
35
34
33
VOUT5
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
VOUT23
VOUT22
VOUT21
VOUT20
V
V
SIGGND2
VOUT19
Clear Function
SS
DD
section for more information.