CDB4398 Cirrus Logic Inc, CDB4398 Datasheet - Page 22

• Manufacturer Part Number: CDB4398
• Description: BOARD EVAL FOR CS4398 DAC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4398

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 192k
• Data Interface: I²C, SPI™
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS4398
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4398
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1155

22
4.6
(100 to 200 kHz)
(50 to 100 kHz)
Double-Speed
(32 to 50 kHz)
Single-Speed
Quad-Speed
rate range)
M3
M1
(sample-
0
0
1
1
0
0
1
1
Mode
Stand-alone Mode Settings
In Stand-Alone mode (also referred to as “Hardware mode”) the device is configured using the M0 through
M3 pins. These pins must be connected to either the VLC supply or ground. The Interface format is set by
pins M0 and M1. The sample rate range/oversampling mode (Single/Double/Quad-Speed mode) and de-
emphasis are set by pins M2 and M3. The settings can be found in Tables 3 and 4.
The following features are always enabled in Stand-Alone mode: Auto-mute on zero data, Auto MUTEC po-
larity detect, ramp volume from mute to 0dB by 1/8th dB steps every LRCK (soft ramp) after reset or clock
mode change, and the fast roll-off interpolation filter is used.
The following features are not available in Stand-Alone mode: DSD mode, Right-Justified 20- and 18-bit se-
rial audio interfaces, MCLK divide-by-2 and MCLK divide-by-3 (allows 1024 and 1152 clock ratios), slow roll-
off interpolation filter, volume control, ATAPI mixing, 48 kHz and 32 kHz de-emphasis, and all other features
enabled by registers that are not mentioned above.
MCLK Ratio
MCLK Ratio
MCLK Ratio
These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit.
* This MCLK ratio limits the audio word length to 16 bits; see Table 1 on page 21
M0
M2
0
1
0
1
0
1
0
1
Sample
(kHz)
176.4
Rate
44.1
88.2
192
32
48
64
96
Single-Speed without De-Emphasis (32 to 50 kHz sample rates)
Single-Speed with 44.1 kHz De-Emphasis; see Figure 17 on page 30
Double-Speed (50 to 100 kHz sample rates)
Quad-Speed (100 to 200 kHz sample rates)
Table 3. Digital Interface Format, Stand-Alone Mode Options
Table 4. Mode Selection, Stand-Alone Mode Options
12.2880*
11.2896*
12.2880
12.2880
11.2896
11.2896
8.1920
8.1920
256x
128x
64x*
Left-Justified, up to 24-bit data
Table 2. Common Clock Frequencies
Right-Justified, 16-bit Data
Right-Justified, 24-bit Data
I²S, up to 24-bit data
Description
12.2880
16.9344
18.4320
12.2880
16.9344
18.4320
16.9344
18.4320
384x
192x
96x
16.3840
22.5792
24.5760
16.3840
22.5792
24.5760
22.5792
24.5760
512x
256x
128x
Description
MCLK (MHz)
24.5760
33.8688
36.8640
24.5760
33.8688
36.8640
33.8688
36.8640
768x
384x
192x
MCLKDIV2
Format
0
1
2
3
32.7680
45.1584
49.1520
32.7680
45.1584
49.1520
45.1584
49.1520
1024x
512x
256x
MCLKDIV3
Figure
CS4398
36.8640
1152x
DS568F1
3
4
5
5
-
-
-
-
-
-
-
-
-