HI5741-EVS Intersil, HI5741-EVS Datasheet

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HI5741-EVS

Manufacturer Part Number
HI5741-EVS
Description
EVALUATION PLATFORM HI5741
Manufacturer
Intersil
Datasheets

Specifications of HI5741-EVS

Number Of Dac's
1
Number Of Bits
14
Outputs And Type
1, Differential
Sampling Rate (per Second)
100M
Data Interface
Parallel
Settling Time
20ns
Dac Type
Current
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
HI5741
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
14-Bit, 100MSPS, High Speed D/A
Converter
The HI5741 is a 14-bit, 100MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 14-bit linearity is maintained along the
entire transfer curve.
Ordering Information
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
HI5741BIB
HI5741BIB-T
HI5741BIBZ
(Note)
HI5741BIBZ-T
(Note)
HI5741-EVS
NUMBER
PART
HI5741BIB
HI5741BIB
HI5741BIBZ
HI5741BIBZ 28 Ld SOIC Tape and Reel
MARKING
PART
®
28 Ld SOIC Tape and Reel M28.3
(Pb-free)
RANGE (°C)
-40 to +85
-40 to +85
1
TEMP.
+25
Data Sheet
28 Ld SOIC M28.3
28 Ld SOIC
(Pb-free)
Evaluation Board
(SOIC)
PACKAGE
M28.3
M28.3
DWG. #
PKG.
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 100MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . . . 1 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . . 1pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Cellular Base Stations
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Test Equipment
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout
Copyright © Intersil Americas Inc. 2000, 2001, 2003, 2004, 2006. All Rights Reserved
September 20, 2006
D13 (MSB)
All other trademarks mentioned are the property of their respective owners.
D0 (LSB)
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
10
11
12
13
14
1
2
3
4
5
6
7
8
9
(28 LD SOIC)
TOP VIEW
HI5741
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DGND
AGND
REF OUT
CTRL AMP OUT
CTRL AMP IN
R
AV
I
I
ARTN
DV
DGND
DV
CLOCK
OUT
OUT
SET
FN4071.12
HI5741
EE
EE
CC

Related parts for HI5741-EVS

HI5741-EVS Summary of contents

Page 1

... HI5741BIBZ-T HI5741BIBZ 28 Ld SOIC Tape and Reel (Note) (Pb-free) HI5741-EVS +25 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B ...

Page 2

... Functional Block Diagram (LSB 14-BIT D6 MASTER REGISTER D10 D11 D12 (MSB) D13 CLK AV AGND DV DGND HI5741 +5V HI5741 0.01µF DV (16) CC D13 D13 (MSB) (1) D12 (2) D12 D11 (3) D11 (24) CTRL AMP IN D10 (4) D10 (25) CTRL AMP OUT D9 ( (6) (26) REF OUT D7 D7 (7) D6 (21 (8) OUT D5 D5 (9) ...

Page 3

... Spurious Free Dynamic Range within a Window (Note 4) 3 HI5741 Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature to -0.5V HI5741BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C CC Maximum Storage Temperature Range . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s +300°C (SOIC - Lead Tips Only -4.94V to -5.46V +4.75 to +5.25V ...

Page 4

... Sine Wave, to -3dB Loss (Note 4) (Note 5) (Note 5) (Note 5) (Note 5) (Note 4) See Figure 1 (Note 4) See Figure 1 (Note 4) See Figure 1 (Note 4) See Figure 1 (Note 4) (Note 5) (Note 5) (Note 5) (Note 5) ±5%, V ± Internal, REF HI5741BI T = -40°C TO +85°C A MIN TYP MAX - ...

Page 5

... I OUT SETT FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM CLK t SU D13-D0 I OUT t PD FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 5 HI5741 50% ERROR BAND FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT t t PW1 PW2 HLD HLD t SETT t PD ...

Page 6

... CODE FIGURE 6. TYPICAL INL PERFORMANCE -50 -40 -30 -20 - TEMPERATURE (°C) FIGURE 8. TYPICAL OFFSET CURRENT OVER TEMPERATURE 6 HI5741 -1.17 -1.18 -1.19 -1.20 -1.21 -1.22 -1.23 -1.24 -1.25 -1.26 -1. -50 -40 -30 -20 -10 FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER 0.8 0.5 0.25 0 -0.25 -0.5 -0 ...

Page 7

... OUT 10 CLK (MSPS) CLK FIGURE 10. SFDR vs CLOCK FREQUENCY MSPS CLK (MSPS) OUT FIGURE 12. SFDR 100 MSPS CLK (MHz) OUT FIGURE 14. SFDR HI5741 (Continued 100 OUT -72 -74 -76 -78 -80 -82 -84 - FIGURE 15. HARMONIC DISTORTION vs CLOCK FREQUENCY OUT OUT 5 CLK (MSPS) CLK FIGURE 11. SFDR vs CLOCK FREQUENCY ...

Page 8

... Control amplifier out. Provides precision control of the current sources when connected to CTRL AMP IN such that I 26 REF OUT -1.23V (typical) bandgap reference voltage output. Can sink up to 500µ overdriven by an external reference capable of delivering up to 2mA. 8 HI5741 (Continued 100 MSPS MTPR = 75.17dBc CLK ...

Page 9

... Clocks and Termination The internal 14-bit register is updated on the rising edge of the clock. Since the HI5741 clock rate can run to 100 MSPS, to minimize reflections and clock noise into the part, proper termination should be used. In PCB layout clock runs should be kept short and have a minimum of loads ...

Page 10

... Settling Time The settling time of the HI5741 is measured as the time it takes for the output of the DAC to settle to within a ±defined error band of its final value during a 0001 0000.... or 1111... to 1110 1111...) scale transition. In defining settling time specifications for the HI5741, two levels of accuracy are considered ...

Page 11

... FIGURE 25. MEASURING GLITCH ENERGY Applications Bipolar Applications To convert the output of the HI5741 to a bipolar 4V swing, the following applications circuit is recommended. The reference can only provide 125µA of drive must be buffered to create the bipolar offset current needed to generate the -2V output with all bits ‘off’. The output current must be converted to a voltage and then gained up and offset to produce the proper swing ...

Page 12

... CLK BASEBAND BIT ENCODER STREAM CONTROLLER FIGURE 27. PSK MODULATOR USING THE HI5741 AND HSP45106 16-BIT NCO 12 HI5741 Multi-Tone Power Ratio (MTPR) is the amplitude difference from peak amplitude to peak distortion (either harmonic or the clock frequency is non-harmonic tone pattern is loaded into the D/A. The tone spacing of this pattern (∆ ...

Page 13

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 HI5741 M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...

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