MAX9939EVKIT+ Maxim Integrated Products, MAX9939EVKIT+ Datasheet - Page 8

• Manufacturer Part Number: MAX9939EVKIT+
• Description: KIT EVAL FOR MAX9939
• Manufacturer: Maxim Integrated Products

Specifications of MAX9939EVKIT+

• Channels Per Ic: 2 - Dual
• Amplifier Type: Programmable Gain
• Output Type: Differential
• Slew Rate: 9 V/µs
• Current - Output / Channel: 70mA
• Operating Temperature: -40°C ~ 125°C
• Current - Supply (main Ic): 3.4mA
• Voltage - Supply, Single/dual (±): 2.9 V ~ 5.5 V
• Board Type: Fully Populated
• Utilized Ic / Part: MAX9939
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -

SPI Programmable-Gain Amplifier
with Input V
CMRR, gain accuracy, and very low temperature drift
due to precise resistor matching. The output of this
amplifier is level shifted to V
This amplifier is followed by a programmable-gain
inverting amplifier (amplifier A) with programmable R
and R
157V/V. The output of this amplifier is biased at
V
temperature drift.
The MAX9939 has an uncommitted op amp (amplifier
B) whose noninverting input is referenced to V
inverting input and output are externally accessible,
allowing it to be configured either as an active filter or
as a differential output.
A robust input ESD protection scheme allows input volt-
ages at INA+ and INA- to reach ±16V without damag-
ing the MAX9939, thus making the part extremely
attractive for use in front-ends that can be exposed to
high voltages during fault conditions. In addition, its
input-voltage range extends down to -V
when powered from a 5V single supply) allowing the
MAX9939 to translate below ground signals to a 0V to
5V output signal. This feature simplifies interfacing
ground-referenced signals with unipolar-input ADCs.
The MAX9939 has a write-only interface, consisting of
three inputs: the clock signal (SCLK), data input (DIN),
and chip-select input (CS). The serial interface works
with the clock polarity (CPOL) and clock phase (CPHA)
both set to 0 (see Figure 1). Initiating a write to the
MAX9939 is accomplished by pulling CS low. Data is
clocked in on the rising edge of each clock pulse, and
is written LSB first. Each write to the MAX9939 consists
Figure 2. SPI Interface Timing Diagram (CPOL = CPHA = 0)
8
CC
_______________________________________________________________________________________
/2 and has extremely high gain accuracy and low
I
resistors whose gain varies between 0.2V/V and
SPI-Compatible Serial Interface
SCLK
DIN
CS
CC
OS
/2.
Trim and Output Op Amp
D0
CC
/2 (e.g., -2.5V
D1
CC
D2
/2. Its
D3
F
D6
of 8 bits (1 byte). Pull CS high after the 8th bit has been
clocked in to latch the data and before sending the
next byte of instruction. Note that the internal register is
not updated if CS is pulled high before the falling edge
of the 8th clock pulse.
The MAX9939 consists of three registers: a shift register
and two internal registers. The shift register accepts
data and transfers it to either of the two internal regis-
ters. The two internal registers store data that is used to
determine the gain, input offset voltage, and operating
modes of the amplifier. The two internal registers are the
Input V
the 8-bit write to these registers is shown in Tables 1
and 2. Data is sent to the shift register LSB first.
SEL: The SEL bit selects which internal register is writ-
ten to. Set SEL to 0 to write bits D5:D1 to the input V
trim register. Set SEL to 1 to write D4:D1 to the Gain
register (D5 is don’t care when SEL = 1).
Table 1. Input V
Table 2. Gain Register
X = Don’t care.
D5
SHDN MEAS
SHDN MEAS
MSB
MSB
D7
D7
D6
OS
D6
D6
D7
Trim register and Gain register. The format of
D5
V4
D5
X
OS
D4
V3
D4
G3
Trim Register
Register Description
D3
V2
D3
G2
D2
D2
G1
V1
D1
D1
G0
V0
SEL = 0
SEL = 1
LSB
LSB
D0
D0
OS