Z8F04328100KIT Zilog, Z8F04328100KIT Datasheet - Page 17

• Manufacturer Part Number: Z8F04328100KIT
• Description: KIT DEV Z8 ENCORE 4K SERIES 28P
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F04328100KIT

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8 Encore! 28-pin
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3389

Schematics
UM018501-1004
D
C
B
A
VCC_33V
TABLE 2
Internal Only
Crystal
Ceramic Res
External CMOS
(Use PA0_T0IN
pin on JP2)
Clock Mode
GND
PA6_nT1OUT
PA7_T1OUT
PC3_COUT
C19
R14
0
GPIO
Analog
Supply
1
PA3_CTS0
PA4_RXD0
Note 2: The 4K does not support an external oscillator even though crystal Y1 is installed.
PB1_ANA1
PB2_ANA2
PB3_ANA3
VCC_33V
PA0_T0IN
PA1_T0OUT
GND
PA2
Y1
1
VCC_33V
GND
1
1
1
D2
GREEN
D3
YELL
D4
RED
TABLE 1
8 MHz
0 Ohm
0 Ohm
none
R14
none
0 ohm
1M
none
R12
R18
3
The following diagrams provide schematics for the Z8 Encore! 4K Series Development Board.
Schematic, Z8 Encore! 4K Series Development Board, Page 1 of 2
10
3
1
2
3
4
5
6
7
8
9
5
5
2
2
2
Z8F04xA
Z8F0423
U6
PB1/ANA1
PB2/ANA2
PB3/CLKIN/ANA3
VDD
PA0/T0IN/T0OUT/XIN/
PA1/T0OUT/XOUT
GND
PA2/DE
PA3/CTS0
PA4/RXD0
220 Ohm
R15
0 ohm
none
none
0 Ohm
none
R13
C20
R15
0
NOTE 2
R7
R8
R10
20 pin footprint
100
10
none
none
R18
none
none
100
none
0 ohm
R16
Yes
none
C19
none
PC0/ANA4/CINP/LED
PC1ANA5/CINN/LED
none
0 ohm
none
R17
PA6/T1IN/T1OUT
VCC_33V
PC3/COUT/LED
PC2/ANA6/LED
RESET/PD0
PA7/T1OUT
PB0/ANA0
PA5/TXD0
none
C20
none
Yes
none
optional
DBG
R9
100K
none
U8
20
19
18
17
16
15
14
13
12
11
Y1
none
Yes
Yes
none
R11
100
PB0_ANA0
PC3_COUT
PC2_ANA6
PC1_ANA5
PC0_ANA4
PA7_T1OUT
PA6_nT1OUT
PA5_TXD0
4
VCC_33V
DBG
PD0
4
GND
Note 2:
ceramic resonator, external R/C and external CMOS drive clock
the clock mode selected.
configured for external 8Mhz ceramic resonator or internal
clock operation.
Table 2 shows the recommended clock mode configurations.
modes.
PA2
TEST
SW2
R16 0
PB0_ANA0
1
The XP supports internal, external crystal, external
R14, R15, R18, C19, C20 and Y1 are used to support
GND
U8
IO
R12
SENSE
NOTE 1:
0
EMI Filter
0.001uF
IO
Note 1:
PB6 and PB7 are dual function pins (GPIO or Analog
Supply)
R12, R13, R16, and R17 are zero-ohm jumpers used in
conjuntion with GPIO Control Registers to select
function desired. The development board is shipped
with jumpers configured for Analog Supply.
U8 is an optional filter that can be used to improve
the quality of the Analog Supply
Table 1 shows the configurations
C10
PB1_ANA1
C11
0.001uF
3
R17 0
PA3_CTS0
PA4_RXD0
PA5_TXD0
NOTE 1:
The development board is shipped
PB2_ANA2
C12
0.001uF
PB2_ANA2
PB4_ANA7
PB5
PB3_ANA3
VCC_33V
PA0_T0IN
PA1_T0OUT
PB7
PRELIMINARY
R13
0
PA2
PA3_CTS0
PA4_RXD0
PA5_TXD0
GND
C13
0.001uF
PB3_ANA3
3
PB6
3
10
11
12
13
14
1
2
3
4
5
6
7
8
9
U5
PB2/ANA2
PB4/ANA7
PB5/Vref
PB3/ANA3/CLKIN
PB6(AVDD)
VDD
PA0/T0IN/T0OUTXIN
PA1/T0OUT/XOUT
GND
PB7(AGND)
PA2/DE
PA3/CTS0
PA4/RXD0
PA5/TXD0
C14
0.001uF
28 pin footprint
PC0_ANA4
Z8F04xA_28
recommended
Z8F0423
C15
0.001uF
PC1_ANA5
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
PA6/T1IN/T1OUT
GND
PC3/COUT/LED
PB0_ANA0
PB1_ANA1
PB2_ANA2
PB3_ANA3
PC0_ANA4
PC1_ANA5
PC2_ANA6
PB4_ANA7
PC2/ANA6/LED
RESET/PD0
PA7/T1OUT
PB1/ANA1
PB0/ANA0
PC7/LED
PC6/LED
PC5/LED
PC4/LED
RESET/TEST2
PC2_ANA6
C16
0.001uF
DBG
SW1
11
13
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
3
5
7
9
JP5
HEADER 2
J2
HEADER 8X2
1
2
PB1_ANA1
PB0_ANA0
PC3_COUT
PC2_ANA6
PC1_ANA5
PC0_ANA4
PA6_nT1OUT
PB4_ANA7
C17
0.001uF
DBG
PD0
PC7
PC6
PA7_T1OUT
PC5
PC4
connector 2
2
4
6
8
10
12
14
16
2
2
C18
0.001uF
GND
R19 10K
DBG
Title
Size
Date:
B
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
XP 4K MDS Processor Module. Schematic.
Document Number
PB4_ANA7
PC1_ANA5
PB3_ANA3
PB1_ANA1
VCC_33V
PC4
PC7
PC3_COUT
PA6_nT1OUT
PA7_T1OUT
PA3_CTS0
PA4_RXD0
PB6
PB7
-RESET
Wednesday, February 25, 2004
GND
GND
VCC_33V
VCC_33V
GND
GND
-TRSTN
-CS2
GND
A21
A22
-CS0
-BUSACK
-F91_WE
A6
A10
A8
A13
A15
A18
A19
A2
A11
A4
A5
D1
D3
D5
D7
-MREQ
-WR
96C0941-001
connector 1
for
reference
only
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
JP2
HEADER 30x2/SM
HEADER 30x2/SM
JP1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Sheet
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
1
-DIS_IrDA
PC2_ANA6
PC0_ANA4
PB2_ANA2
PB0_ANA0
VCC_33V
VCC_33V
-DIS_FLASH
VCC_33V
A0
A3
A14
A16
A23
-CS1
GND
A7
A9
A17
D0
D2
D4
D6
-IOREQ
-RD
-INSTRD
-BUSREQ
GND
PC5
PC6
PA1_T0OUT
PA5_TXD0
GND
A1
A12
A20
PB5
PA0_T0IN
PA2
PD0
GND
1
User Manual
GND
GND
of
Schematics
-DIS_232
-DIS_IRDA
2
Rev
B
D
C
B
A
11