IDT72261 IDT [Integrated Device Technology], IDT72261 Datasheet
IDT72261
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IDT72261 Summary of contents
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... The IDT72261/72271 have two modes of operation: In the IDT Standard Mode , the first word written to the FIFO is deposited into the memory array. A read operation is required to access that word. In the First Word Fall Through Mode ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 state of the FWFT/SI pin during Master Reset determines the mode in use. The IDT72261/72271 FIFOs have five flag functions, OR (Empty Flag or Output Ready), HF Ready), and (Half-full Flag). The selected in the IDT Standard Mode The and ...
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... The FS line ensures optimal data flow through the FIFO tied to GND if the RCLK frequency is higher than the WCLK frequency or to Vcc if the RCLK frequency is lower than the WCLK frequency The IDT72261/72271 is fabricated using IDT’s high speed submicron CMOS technology ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable OE Output Enable SEN ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial V Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 TERM with respect to GND T Operating 0 to +70 A Temperature T Temperature Under –55 to +125 –65 to +135 BIAS Bias T Storage –55 to +125 –65 to +155 STG Temperature I DC Output Current ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 ELECTRICAL CHARACTERISTICS (Commercial 10 +70 C; Military Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time CLKL t Data Set-up Time DS t Data Hold Time ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 SIGNAL DESCRIPTIONS: INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MRS MRS MASTER RESET ( ) A Master Reset is accomplished whenever the Master MRS Reset ( ) input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 When goes LOW, Retransmit Setup is complete; at the same time, the contents of the first location are automatically displayed on the outputs. Since FWFT Mode is selected, the first word appears on the outputs, no read request necessary. Reading all subsequent words requires a LOW on enable the rising edge of RCLK ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 SEN SEN SERIAL ENABLE ( ) SEN Serial Enable enable used only for serial programming of the offset registers. The serial programming method must be selected during Master Reset. LD used in conjunction with . When these lines are both LOW, data at the SI input can be loaded into the input register one bit for each LOW-to-HIGH transition of WCLK ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers. A Master Reset initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has no effect on the position of these pointers. Once serial offset loading has been selected, then pro- ...
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... LOW when memory space is available for writing in data. When there is no longer any free space left, HIGH, inhibiting further write operation reads are MRS performed after a reset (either after 16,385 writes for the IDT72261 and 32,769 writes for the IDT72271. 72261 – 16,384 x 9–BIT 8 7 EMPTY OFFSET (LSB) REG ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 FWFT Mode, the Ouput Ready ( OR goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. cycle after RCLK shifts the last word from the FIFO memory to the outputs. Then further data reads are inhibited until goes LOW again ...
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... In IDT Standard Mode reads are performed after reset MRS PAE PAE ( or ) PAE is the maximum FIFO depth ( 16,384 words for the IDT72261, ) will go LOW 32,768 words for the IDT72271). In FWFT Mode reads are performed after reset ( PRS 72271 ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 MRS REN WEN t FWFT FWFT/SI LD (1) RT SEN PAE PAF MILITARY AND COMMERCIAL TEMPERATURE RANGES RSS t t RSS RSS t RSS t RSS t RSF If FWFT = HIGH, If FWFT = LOW, t RSF If FWFT = LOW, ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 PRS REN WEN RT SEN PAE PAF RSS RSR t t RSS RSR t RSS t RSS t RSF If FWFT = HIGH, If FWFT = LOW, t RSF If FWFT = LOW, If FWFT = HIGH, t RSF t RSF t RSF Figure 5. Partial Reset Timing ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 CLK t CLKH 1 WCLK WEN FF (1) t SKEW1 RCLK REN NOTES the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that SKEW1 If the time between the rising edge of RCLK and the rising edge of WCLK is less than t cycle ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 RCLK t t ENS REN OLZ OE WCLK WEN NOTES contributes a variable delay to the overall first word latency (this parameter includes delays due to skew): FWL1 t max. (in ns FWL1 f RCLK where T ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK first valid write t ENS WEN t FWL1 RCLK EF REN NOTES max. (in ns FWL1 f RCLK Where T is either the RCLK or the WCLK period, whichever is shorter, and ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t ENH t ENS REN OE LOW DATA IN OUTPUT REGISTER 0 8 NOTES the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that SKEW1 If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than t WCLK cycle ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK t DS DATA WRITE ENH ENS WEN (1) t FWL1 RCLK EF REN OE LOW DATA IN OUTPUT REGISTER NOTES max. (in ns) = 10*T + 2*T FWL1 f RCLK Where T is either the RCLK or the WCLK period, whichever is shorter, and T ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK t t ENS ENH SEN t t LDS LDH BIT 0 EMPTY OFFSET (LSB) Figure 11. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT modes) NOTE: 1. For the 72261 For the 72271 CLK ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 CLK t t CLKH CLKL RCLK t LDS LD t ENS REN DATA IN OUTPUT REGISTER Figure 13. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT modes) NOTES LOW t CLKL t CLKH WCLK t t ENS ENH WEN PAE ...
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... Figure 15. Programmable Almost Full Flag Timing (IDT Standard and FWFT modes) WCLK WEN HF D/2 words RCLK REN NOTES maximum FIFO depth = 16,384 for IDT72261, 32,768 words for IDT72271. Figure 16. Half - Full Flag Timing (IDT Standard and FWFT modes PAF words in FIFO memory ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK ENH RTS ENS WEN RCLK t t ENS t ENH RTS REN ENS RT EF PAE HF PAF FF (4) NOTES contributes a variable delay to the overall retransmit recovery time: ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES 25 ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES 26 ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK ENH RTS ENS WEN RCLK t t ENS t ENH RTS REN ENS RT OR PAE HF PAF (4) IR NOTES contribute a variable delay to the overall retransmit time: ...
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... IDT Standard mode, such problems can be avoided by creat- ing composite flags, that is, ANDing separately ANDing EF posite flags can be created by ORing IR OR and separately ORing an 18-word width by using two IDT72261/72271s. Any word deassertion width can be attained by adding additional IDT7226172271s. MILITARY AND COMMERCIAL TEMPERATURE RANGES MRS ) ...
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... Do not connect any output control signals directly together. Figure 22. Block Diagram of 16,384x18/32,768x18 72261/71 Width Expansion DEPTH EXPANSION CONFIGURATION The IDT72261/72271 can easily be adapted to applications requiring more than 16,384/32,768 words of buffering. In FWFT mode, the FIFOs can be arranged in series (the data outputs of one FIFO connected to the data inputs of the next)– ...
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... IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 where T is the RCLK period and T RCLK the WCLK period, whichever is shorter. The maximum amount of time it takes for a word to pass from the inputs of the first FIFO to the outputs of the last FIFO in the chain is the sum of the delays for each individual FIFO: ...