SSTUA32866 Philips Semiconductors, SSTUA32866 Datasheet
SSTUA32866
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SSTUA32866 Summary of contents
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... C0 and C1) to two topologies: 25-bit 14-bit and in the latter configuration can be designated as Register A or Register B on the DIMM. The SSTUA32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defi ...
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... Pb-free (SnAgCu solder ball compound) SSTUA32866EC SnPb solder ball compound 5. Functional diagram (1) Disabled configuration. Fig 1. Functional diagram of SSTUA32866 Register A configuration with and 9397 750 14759 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity Package Name Description LFBGA96 plastic low profi ...
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... D8 to D14 PARITY CHECK CLK CLK CLK 2-BIT LPS1 COUNTER (internal node) R Rev. 01 — 15 July 2005 SSTUA32866 Q2A, Q3A, Q5A, Q6A, D2, D3, D5, D6, 11 Q8A to Q14A D8 to D14 11 11 Q2B, Q3B, Q5B, Q6B, Q8B to Q14B CLK CLK ...
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... D21 GND GND N D11 D22 D12 D23 GND GND R D13 D24 D14 D25 VREF V DD Rev. 01 — 15 July 2005 SSTUA32866 QCKE DNU Q2 Q15 Q3 Q16 QODT DNU Q5 Q17 Q6 Q18 C1 C0 QCS DNU n.c. n.c. Q8 Q19 Q9 Q20 Q10 Q21 Q11 ...
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... DODT DNU D12 DNU GND GND R D13 DNU DCKE DNU VREF V DD Rev. 01 — 15 July 2005 SSTUA32866 5 6 QCKEA QCKEB Q2A Q2B Q3A Q3B QODTA QODTB Q5A Q5B Q6A Q6B C1 C0 QCSA QCSB n.c. n.c. Q8A Q8B Q9A Q9B ...
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... V CMOS output [1] 1.8 V CMOS output [1] 1.8 V CMOS output Rev. 01 — 15 July 2005 SSTUA32866 Description ground power supply voltage input reference voltage positive master clock input negative master clock input Configuration control inputs; Register A or Register B and mode mode select. ...
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... Data outputs = Q10, Q12, Q13 when and Functional description The SSTUA32866 is a 25-bit 14-bit configurable registered buffer with parity, designed for 1 2 All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS ...
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... As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUA32866 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. ...
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... floating X or floating = LOW-to-HIGH transition; Inputs the previous state of output QERR. 0 Rev. 01 — 15 July 2005 SSTUA32866 = HIGH-to-LOW transition Outputs Dn, DODTn, Qn QCS DCKEn ...
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... CSR, - and PAR_IN inputs data (Dn), CSR 0.125 ref and PAR_IN inputs data (Dn), CSR, - and PAR_IN inputs [1] RESET, Cn 0.65 [1] RESET [2] CK, CK 0.675 [2] CK, CK 600 Rev. 01 — 15 July 2005 SSTUA32866 Min Max 0.5 +2.5 [1] [2] 0.5 +2.5 [ 100 65 +150 2 - 200 - Typ ...
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... One data input switching at half clock frequency duty cycle mA 1 250 mV 1 ref 0 600 mV; ICR i(p- 1 GND 1 Rev. 01 — 15 July 2005 SSTUA32866 Typ Max - +70 Min Typ Max 1 0 100 - - 40 IL(AC ...
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... CK and CK to QERR from CK and from RESET to Qn from RESET to PPO from RESET to QERR Table 6), unless otherwise specified. See Conditions from from from Rev. 01 — 15 July 2005 SSTUA32866 Figure 2. Min Typ Max - - 450 [1] [2] ...
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... DCS CSR D25 Q25 PAR_IN PPO QERR Fig 7. Timing diagram for SSTUA32866 used as a single device 9397 750 14759 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity ...
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... D14 Q14 PAR_IN PPO QERR (not used) Fig 8. Timing diagram for the first SSTUA32866 ( Register A configuration) device used in pair 9397 750 14759 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity ...
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... PPO (not used) QERR (1) PAR_IN is driven from PPO of the first SSTUA32866 device. Fig 9. Timing diagram for the second SSTUA32866 ( Register B configuration) device used in pair 9397 750 14759 Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity ...
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... ICR V = 600 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref Rev. 01 — 15 July 2005 SSTUA32866 20 %, unless otherwise specified. DUT T = 350 ps OUT ( ...
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... PLH PHL 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref Rev. 01 — 15 July 2005 SSTUA32866 V V ICR ref V IL 002aaa374 = V for LVCMOS inputs. ...
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... V DDR2-667 configurable registered buffer with parity 0 input slew rate = 1 V/ns 0 DUT OUT includes probe and jig capacitance. L output dv_f DUT OUT includes probe and jig capacitance. L dv_r output Rev. 01 — 15 July 2005 SSTUA32866 20 %, unless otherwise specified test point ( 002aaa377 ...
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... L LVCMOS RESET PLH output waveform 2 RESET input. timing V ICR inputs t HL output waveform 1 to clock inputs Rev. 01 — 15 July 2005 SSTUA32866 20 %, unless otherwise specified test point ( 002aaa500 0. ...
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... CK V ICR CK t PLH output and t are the same PLH PHL 600 mV i(p-p) inputs Rev. 01 — 15 July 2005 SSTUA32866 V V i(p-p) ICR 002aaa503 20 %, unless otherwise specified. test point ( 002aaa654 V V i(p-p) ICR ...
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... PLH PHL 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref RESET input Rev. 01 — 15 July 2005 SSTUA32866 PHL 002aaa376 = V for LVCMOS inputs ...
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... 5.6 13.6 0 0.15 5.4 13.4 REFERENCES JEDEC JEITA Rev. 01 — 15 July 2005 SSTUA32866 detail 0.1 0.1 0.2 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT536-1 ISSUE DATE 00-03-04 03-02- ...
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... Product data sheet 1.8 V DDR2-667 configurable registered buffer with parity 2 called small/thin packages. Rev. 01 — 15 July 2005 SSTUA32866 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 01 — 15 July 2005 SSTUA32866 Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] not recommended suitable ...
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... Partial Parity Out Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic Data sheet status Change notice Product data sheet - Rev. 01 — 15 July 2005 SSTUA32866 Doc. number Supersedes 9397 750 14759 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 01 — 15 July 2005 SSTUA32866 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands SSTUA32866 Date of release: 15 July 2005 Document number: 9397 750 14759 ...