PIC16F505-I/P Microchip Technology, PIC16F505-I/P Datasheet
PIC16F505-I/P
Specifications of PIC16F505-I/P
Related parts for PIC16F505-I/P
PIC16F505-I/P Summary of contents
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... Flash Microcontrollers © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Data Sheet DS41236E ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Direct, Indirect and Relative Addressing modes for Data and Instructions • 8-Bit Wide Data Path • 8 Special Function Hardware Registers • Operating Speed – 20 MHz clock input (PIC16F505 only – 200 ns instruction cycle (PIC16F505 only – 4 MHz clock input - DC – 1000 ns instruction cycle Special Microcontroller Features: • ...
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... Pin Diagrams PDIP, SOIC, TSSOP RB5/OSC1/CLKIN RB4/OSC2/CLKOUT 12 RB3/MCLR RC5/T0CKI 6 9 RC4 RC3 8 7 DFN V DD GP5/OSC1/CLKIN GP4/OSC2 GP3/MCLR/V PP PIC16F505 16-Pin Diagram (QFN) RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR/V RC5/TOCKI DS41236E-page 4 PDIP, SOIC, MSOP RB0/ICSPDAT GP5/OSC1/CLKIN RB1/ICSPCLK GP4/OSC2 RB2 GP3/MCLR/V PP RC0 RC1 RC2 GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI ...
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... Program Memory Device Flash (words) PIC12F508 PIC12F509 PIC16F505 © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Data Memory SRAM (bytes) 512 25 1024 41 1024 72 Timers I/O 8-bit DS41236E-page 5 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS41236E-page 6 © 2009 Microchip Technology Inc. ...
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... The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for exter- nal Reset circuitry. There are four oscillator configura- tions to choose from (six on the PIC16F505), including INTRC Internal Oscillator mode and the power-saving LP (Low-Power) Oscillator mode. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability ...
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... PIC12F508/509/16F505 NOTES: DS41236E-page 8 © 2009 Microchip Technology Inc. ...
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... Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 2 ...
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... PIC12F508/509/16F505 NOTES: DS41236E-page 10 © 2009 Microchip Technology Inc. ...
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... Device Program PIC12F508 512 x 12 PIC12F509 1024 x 12 PIC16F505 1024 x 12 The PIC12F508/509/16F505 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC12F508/509/ 16F505 devices have a highly orthogonal (symmetri- ...
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... RAM Stack 1 Stack 2 File Registers RAM Addr 9 Addr MUX Indirect 5 Direct Addr 5-7 Addr FSR Reg Status Reg 3 MUX Device Reset Timer ALU Power-on Reset 8 Watchdog W Reg Timer Timer0 GPIO GP0/ISCPDAT GP1/ISCPCLK GP2/T0CKI GP3/MCLR/V PP GP4/OSC2 GP5/OSC1/CLKIN © 2009 Microchip Technology Inc. ...
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... Legend Input Output, I/O = Input/Output Power, — = Not used, TTL = TTL input Schmitt Trigger input High Voltage © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Output Type TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ...
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... PIC12F508/509/16F505 FIGURE 3-2: PIC16F505 BLOCK DIAGRAM 12 Program Counter Flash Program Memory Program 12 Bus Instruction Reg Direct Addr 8 Device Reset Instruction Decode and Control Timing OSC1/CLKIN Generation OSC2/CLKOUT MCLR DS41236E-page 14 8 Data Bus RAM Stack 1 File Stack 2 Registers RAM Addr 9 Addr MUX ...
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... TABLE 3-3: PIC16F505 PINOUT DESCRIPTION Input Name Function Type RB0/ICSPDAT RB0 ICSPDAT RB1/ICSPCLK RB1 ICSPCLK RB2 RB2 RB3/MCLR/V RB3 PP MCLR V PP RB4/OSC2/CLKOUT RB4 OSC2 CLKOUT RB5/OSC1/CLKIN RB5 OSC1 XTAL CLKIN RC0 RC0 RC1 RC1 RC2 RC2 RC3 RC3 RC4 RC4 RC5/T0CKI ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Fetch INST ( Execute INST (PC) Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal phase clock Fetch INST ( Execute INST ( Flush Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... Program memory pages are accessed using one STATUS register bit. For the PIC12F509 and PIC16F505, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR) ...
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... For the PIC12F508/509, the register file is composed of 7 Special Function Registers, 9 General Purpose Registers and General Purpose Registers accessed by banking (see Figure 4-3 and Figure 4-4). For the PIC16F505, the register file is composed of 8 Special Function Registers, 8 General Purpose Registers and 64 General Purpose Registers accessed by banking (Figure 4-5). ...
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... OSCCAL 05h GPIO 06h 07h General Purpose Registers 1Fh Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”. FIGURE 4-5: PIC16F505 REGISTER FILE MAP FSR<6:5> 00 File Address (1) 00h INDF 01h TMR0 02h PCL 03h STATUS ...
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... GP3 GP2 GP1 I/O Control Register PSA PS2 PS1 Value on Power-On Page # (2) Reset 28 xxxx xxxx 35 xxxx xxxx 27 1111 1111 ( 0-01 1xxx 28 111x xxxx 28 110x xxxx — 26 1111 111- GP0 31 --xx xxxx 31 --11 1111 PS0 24 1111 1111 © 2009 Microchip Technology Inc. ...
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... TABLE 4-2: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505) Address Name Bit 7 Bit 6 00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) 01h TMR0 8-bit Real-Time Clock/Counter (1) 02h PCL Low-order 8 bits of PC 03h STATUS RBWUF — 04h FSR Indirect Data Memory Address Pointer ...
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... Status bits, see Section 8.0 “Instruction Set Summary”. R-1 R-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) RRF or RLF: SUBWF borrow did not occur Load bit with LSb or MSb, respectively borrow occurred R/W-x R/W bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... REGISTER 4-2: STATUS REGISTER (ADDRESS: 03h) (PIC16F505) R/W-0 R/W-0 R/W-0 RBWUF — PA0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBWUF: PORTB Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset ...
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... If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin. W-1 W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4 OSC 128 256 1 : 128 W-1 W-1 W-1 PS2 PS1 PS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... REGISTER 4-4: OPTION REGISTER (PIC16F505) W-1 W-1 W-1 RBWU RBPU T0CS bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4 Disabled 0 = Enabled bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4) ...
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... After you move in the calibration constant, do not change the value. See Section 7.2.5 “Internal 4 MHz RC Oscillator”. R/W-1 R/W-1 R/W-1 CAL3 CAL2 CAL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-1 CAL0 — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PCL Instruction Word Reset to ‘0’ PA0 7 0 Status © 2009 Microchip Technology Inc. PIC12F508/509/16F505 4.7.1 EFFECTS OF RESET The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code ...
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... PIC12F508 – Does not use banking. FSR <7:5> are unimplemented and read as ‘1’s. PIC12F509 – Uses FSR<5>. Selects between bank 0 and bank 1. FSR<7:6> are unimplemented, read as ‘1’. PIC16F505 – Uses FSR<6:5>. Selects from bank 0 to bank 3. FSR<7> is unimplemented, read as ‘1’. (opcode ...
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... FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505) Direct Addressing (FSR (opcode) Bank Select Location Select 00h Data 0Fh (1) Memory 10h Note 1: For register map detail, see Section 4.3 “Data Memory Organization”. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Addresses map back to addresses in Bank 0. ...
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... PIC12F508/509/16F505 NOTES: DS41236E-page 30 © 2009 Microchip Technology Inc. ...
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... Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set. Note: On the PIC12F508/509, I/O PORTB is ref- erenced as GPIO. On the PIC16F505, I/O PORTB is referenced as PORTB. 5.1 PORTB/GPIO PORTB/GPIO is an 8-bit I/O register. Only the low- order 6 bits are used (RB/GP< ...
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... Shaded cells are not used by Port registers, read as ‘0’. – = unimplemented, read as ‘0’ unknown unchanged depends on condition. Note 1: PIC12F508/509 only. 2: PIC16F505 only Reset was due to wake-up on pin change, then bit All other Resets will cause bit DS41236E-page 32 Bit 5 Bit 4 ...
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... A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired OR”, “wired AND”). The resulting high output currents may damage the chip. FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC16F505 Shown Instruction Fetched ...
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... PIC12F508/509/16F505 NOTES: DS41236E-page 34 © 2009 Microchip Technology Inc. ...
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... Fetch Timer0 Instruction Executed © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restric- tions on the external clock input are discussed in detail in Section 6.1 “ ...
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... N/A TRISGPIO — (2), (3) N/A TRISC — Legend: Shaded cells are not used by Timer0. – = unimplemented unknown unchanged. Note 1: PIC12F508/509 only. 2: PIC16F505 only. 3: The TRIS of the T0CKI pin is overridden when T0CS = 1. DS41236E-page NT0 Write TMR0 Read TMR0 Read TMR0 executed reads NT0 ...
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... Timer0 input = ± External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical ...
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... WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. EXAMPLE 6-2: CHANGING PRESCALER (WDT → TIMER0) CLRWDT ;Clear WDT and ;prescaler MOVLW ‘xxxx0xxx’ ;Select TMR0, new ;prescale value and ;clock source OPTION © 2009 Microchip Technology Inc. ...
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... OSC (GP2/RC5)/T0CKI pin T0SE Watchdog Timer PSA WDT Enable bit Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Sync Cycles ...
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... PIC12F508/509/16F505 NOTES: DS41236E-page 40 © 2009 Microchip Technology Inc. ...
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... The PIC12F508/509/16F505 devices have a Watchdog Timer, which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS (PIC16F505 selectable oscillator options, there is always (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable ...
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... Refer to the “PIC12F508/509 Memory Programming Specifications” (DS41227) to determine how to access the Configuration Word. The Configuration Word is not user addressable during device operation. DS41236E-page 42 (1) — — — MCLRE Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared DD WDTE FOSC1 FOSC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Refer to the “PIC16F505 Memory Programming Specifications” (DS41226) to determine how to access Note 1: the Configuration Word. The Configuration Word is not user addressable during device operation. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 (1) — ...
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... External High-Speed Clock Input (PIC16F505 only) 7.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In HS (PIC16F505 modes, a crystal or ceramic resonator is connected to the (GP5/RB5)/ OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins to establish oscillation (Figure 7-1). The PIC12F508/ 509/16F505 oscillator designs require the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications ...
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... Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 3: PIC16F505 only. 7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit ...
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... See Register 4-5 for more information. Internal clock Note: The 0 bit of OSCCAL is unimplemented and should be written as ‘0’ when modifying OSCCAL for compatibility with PIC16F505 future devices. PIC12F508 PIC12F509 for © 2009 Microchip Technology Inc. ...
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... If Reset was due to wake-up on pin change, then bit All other Resets will cause bit PIC12F509 only. 5: PIC12F508 only. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset. Most other registers are reset to “Reset state” on Power-on Reset (POR), MCLR, WDT or Wake-up on pin change Reset during normal operation ...
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... PIC12F508/509/16F505 TABLE 7-4: RESET CONDITIONS FOR REGISTERS – PIC16F505 Register Address W — INDF 00h TMR0 01h PC 02h STATUS 03h FSR 04h OSCCAL 05h PORTB 06h PORTC 07h OPTION — TRISB — TRISC — Legend unchanged unknown, – = unimplemented bit, read as ‘0’ value depends on condition. ...
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... Reset until the operating parameters are met. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 7-7. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 The Power-on Reset circuit and the Device Reset Timer (see Section 7.5 “Device Reset Timer (DRT)”) circuit are closely related ...
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... DRT Time-out Internal Reset FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V TIME V DD MCLR Internal POR DRT Time-out Internal Reset DS41236E-page 50 POR (Power-on Reset) MCLR Reset Start-up Timer (10 μ ms) TDRT CHIP Reset TDRT ): FAST V RISE DD DD © 2009 Microchip Technology Inc. ...
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... V DD MCLR Internal POR DRT Time-out Internal Reset Note: When V rises slowly, the T DD value. In this example, the chip will reset properly if, and only if, V1 ≥ V © 2009 Microchip Technology Inc. PIC12F508/509/16F505 V1 TDRT time-out expires long before V DRT DD ): SLOW V RISE DD DD has reached its final min ...
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... INTOSC, EXTRC ( XT, LP (1) min. and EC DD Note 1: PIC16F505 only. 7.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with no prescaler longer time-out period is desired, a MCLR) level. prescaler with a division ratio 1:128 can be as MCLR and assigned to the WDT (under software control) by writing to the OPTION register ...
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... Bit 6 (1) N/A OPTION GPWU GPPU T0CS (2) N/A OPTION RBWU RBPU Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’ unchanged. Note 1: PIC12F508/509 only. 2: PIC16F505 only. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 0 M Postscaler Postscaler 8-to-1 MUX PSA To Timer0 0 ...
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... Microchip Technology’s MCP809 micro- controller supervisor. There are 7 different trip point selections to accommodate systems. goes DD BROWN-OUT PROTECTION CIRCUIT PIC16F505 PIC12F508 Q1 (2) PIC12F509 MCLR (1) 40k is below a certain level such 0. BROWN-OUT PROTECTION CIRCUIT MCLR PIC16F505 PIC12F508 PIC12F509 © 2009 Microchip Technology Inc. ...
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... Sleep, a wake-up will occur immediately even if no pins change while in Sleep mode. The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 7.10 Program Verification/Code Protection If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes ...
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... PIC12F508/509/16F505 FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector Signals + MCLR/V PP GP1/RB1 CLK Data I/O GP0/RB0 Normal Connections DS41236E-page 56 PIC16F505 PIC12F508 PIC12F509 PP © 2009 Microchip Technology Inc. ...
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... Register bit field ∈ In the set of User defined term (font is courier) italics © 2009 Microchip Technology Inc. PIC12F508/509/16F505 All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods ...
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... TO PD 0000 0000 0100 , 2 None 101k kkkk kkkk 1 Z 1101 kkkk kkkk 1 None 1100 kkkk kkkk 1 None 0000 0000 0010 2 None 1000 kkkk kkkk 0000 0000 0011 , 1 None 0000 0000 0fff 1 Z 1111 kkkk kkkk © 2009 Microchip Technology Inc. Notes ...
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... The contents of the W register are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 BCF Bit Clear f Syntax: [ label ] BCF 0 ≤ ...
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... Operands: d ∈ [0,1] (f) → (dest) Operation: Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. ...
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... Status Affected: None Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a two- cycle instruction. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 INCF Increment f Syntax: [ label ] INCF f,d 0 ≤ f ≤ 31 Operands: d ∈ ...
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... NOP Operands: None Operation: No operation Status Affected: None Description: No operation. OPTION Load OPTION Register Syntax: [ label ] OPTION Operands: None (W) → OPTION Operation: Status Affected: None Description: The content of the W register is loaded into the OPTION register. © 2009 Microchip Technology Inc. f ...
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... Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. register ‘f’ C © 2009 Microchip Technology Inc. PIC12F508/509/16F505 SLEEP Syntax: Operands: Operation: Status Affected: TO, PD, RBWUF ...
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... Operation: Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. f,d ...
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... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2009 Microchip Technology Inc. PIC12F508/509/16F505 9.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool PC-hosted environment by ® DSCs on an © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC12F508/509/16F505 9.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
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... ICs, CAN, IrDA EE OQ ® battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. © 2009 Microchip Technology Inc. kits and ® , PowerSmart ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 ............................................................................... -0. )...................................................................................................................± ...
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... V DD (Volts) 4.0 3.5 3.0 2.5 2.0 0 FIGURE 10-2: MAXIMUM OSCILLATOR FREQUENCY TABLE LP XT INTOSC EXTRC ( 200 kHz Note 1: For PIC16F505 only. DS41236E-page 70 (PIC16F505 only Frequency (MHz) 4 MHz Frequency (MHz) ≤ +125° MHz © 2009 Microchip Technology Inc. ...
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... V/ms See Section 7.4 "Power-on Reset (POR)" for details μ MHz 2.0V OSC MHz 5.0V OSC DD μ MHz 3.0V OSC MHz 5.0V OSC DD (PIC16F505 only) μ kHz 2.0V OSC DD μ kHz 5.0V OSC DD μ 2.0V DD μ 5.0V DD μ 2.0V DD μ ...
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... Reset (POR)" for details See Section 7.4 "Power-on Reset (POR)" for details MHz 2.0V OSC MHz 5.0V OSC MHz 3.0V OSC MHz 5.0V OSC DD (PIC16F515 only kHz 2.0V OSC kHz 5.0V OSC T0CKI = V , MCLR = SS DD © 2009 Microchip Technology Inc. ...
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... GP3/MCLR is configured as GP3 with a weak pull-up or enabled as MCLR. 5: This specification applies when GP3/RB3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) -40°C ≤ T ≤ ...
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... Max. 186K 187K 190K 190K 33K 34K 35K 35K 96K 116K 116K 119K 22K 23K 28K 29K © 2009 Microchip Technology Inc. ...
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... Uppercase letters and their meanings Fall H High I Invalid (high-impedance) L Low FIGURE 10-3: LOAD CONDITIONS – PIC12F508/509/16F505 pin FIGURE 10-4: EXTERNAL CLOCK TIMING – PIC12F508/509/16F505 Q4 OSC1 © 2009 Microchip Technology Inc. PIC12F508/509/16F505 T Time mc MCLR osc Oscillator os OSC1 t0 T0CKI wdt Watchdog Timer P Period R Rise ...
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... MHz XT Oscillator mode DC — 20 MHz EC, HS Oscillator mode DC — 200 kHz (2) — — 4 MHz EXTRC Oscillator mode 0.1 — 4 MHz XT Oscillator mode 4 — 20 MHz HS Oscillator mode (PIC16F505 — — 200 kHz (2) 250 — — — — ns μs 5 — — 250 — — ...
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... I/O Pin Old Value (output) Note: All tests must be done with specified capacitive loads (see data sheet I/O pins and CLKOUT. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) -40°C ≤ T Operating Temperature -40°C ≤ T Freq Min. Typ† ...
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... Watchdog Timer Reset (1) I/O pin Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT Reset only in XT, LP and HS (PIC16F505) modes. DS41236E-page 78 -40°C ≤ T ≤ +85°C (industrial) A -40°C ≤ T ≤ +125°C (extended) A range is described in Section 10.1 " ...
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... These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ T -40° ...
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... Section 10.1 "Power-on Reset (POR)" Min. Typ No Prescaler 0 20* CY With Prescaler 10* No Prescaler 0 20* CY With Prescaler 10 40 (1) Max. Units Conditions — — ns — — ns — — ns — — ns — — ns Whichever is greater Prescale Value (1, 2, 4,..., 256) © 2009 Microchip Technology Inc. ...
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... 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1,000 800 600 400 200 0 2.0 2.5 © 2009 Microchip Technology Inc. PIC12F508/509/16F505 = 4 MHz OSC 4 MHz 4 MHz 3.0 3.5 4.0 V (V) DD Maximum Typical 4.5 5.0 5.5 DS41236E-page 81 ...
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... Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 DS41236E-page 82 ( PIC16F505 only) DD ODE Max. 3V Typical Fosc (MHz) vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD Typical (Sleep Mode all Peripherals Disabled) 3.0 3.5 4 ...
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... Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 7 (-40°C to 125° 2.0 2.5 © 2009 Microchip Technology Inc. PIC12F508/509/16F505 vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD Maximum (Sleep Mode all Peripherals Disabled) Max. 125°C Max. 85°C 3.0 3.5 4.0 V ...
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... Maximum Max. 125°C Max. 85°C 3.0 3.5 4.0 V (V) DD (1) Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.0 3.5 4.0 V (V) DD 4.5 5.0 5.5 OVER TEMPERATURE (NO DD 4.5 5.0 5.5 © 2009 Microchip Technology Inc. ...
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... Maximum: Mean (Worst-Case Temp) + 3σ Maximum: Meas + 3 (-40°C to 125°C) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 5.0 5.5 6.0 © 2009 Microchip Technology Inc. PIC12F508/509/16F505 = 3.0V) DD (VDD = 3V, -40×C TO 125×C) Typical 25°C Min. -40°C 6.5 7.0 7.5 8.0 I (mA ...
Page 86
... DS41236E-page 86 = 3.0V) DD -1.5 -2.0 -2.5 I (mA 5.0V -1.5 -2.0 -2.5 -3.0 -3.5 I (mA) OH Max. -40°C Typ. 25°C Min. 125°C -3.0 -3.5 -4.0 Max. -40°C Typ. 25°C Min. 125°C -4.0 -4.5 -5.0 © 2009 Microchip Technology Inc. ...
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... Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.0 2.5 2.0 1.5 1.0 0.5 2.0 2.5 © 2009 Microchip Technology Inc. PIC12F508/509/16F505 vs (TTL Input, -40×C TO 125×C) Max. -40°C Typ. 25°C Min. 125°C 3.0 3.5 4.0 ...
Page 88
... PIC12F508/509/16F505 FIGURE 11-14: TYPICAL INTOSC FREQUENCY CHANGE 2.5 2.5 2 FIGURE 11-15: TYPICAL INTOSC FREQUENCY CHANGE 2.5 2.5 2 DS41236E-page 3.5 4 4.5 3 3.5 4 4 3.5 4 4.5 3 3.5 4 4.5 V (V) DD (25°C) 5 5.5 (-40°C) 5 5.5 5 5.5 © 2009 Microchip Technology Inc. ...
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... FIGURE 11-16: TYPICAL INTOSC FREQUENCY CHANGE 2.5 2.5 2 FIGURE 11-17: TYPICAL INTOSC FREQUENCY CHANGE 2.5 2.5 2 © 2009 Microchip Technology Inc. PIC12F508/509/16F505 DD 3 3.5 4 4.5 3 3.5 4 4 4.5 4.5 3 3.5 V (V) DD (85°C) 5 5.5 5.5 5 (125° 5.5 5.5 DS41236E-page 89 ...
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... PIC12F508/509/16F505 NOTES: DS41236E-page 90 © 2009 Microchip Technology Inc. ...
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... Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 Example ...
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... TABLE 12-1: 8-LEAD 2X3 DFN (MC) TOP MARKING Part Number PIC12F508 (T) - I/MC PIC12F508-E/MC PIC12F509 (T) - I/MC PIC12F509-E/MC DS41236E-page 92 Example PIC16F505 e -I/P 3 0215 0610017 Example PIC16F505-E /SL0125 0610017 Example 16F505-I 0610 017 Example 16F505 -I/MG 0610017 Marking BN0 BP0 BQ0 BR0 © 2009 Microchip Technology Inc. ...
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... N NOTE © 2009 Microchip Technology Inc. PIC12F508/509/16F505 DS41236E-page 93 ...
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... PIC12F508/509/16F505 N NOTE DS41236E-page φ α c β © 2009 Microchip Technology Inc. ...
Page 95
... Microchip Technology Inc. PIC12F508/509/16F505 DS41236E-page 95 ...
Page 96
... PIC12F508/509/16F505 D N NOTE DS41236E-page φ L © 2009 Microchip Technology Inc. ...
Page 97
... D N NOTE TOP VIEW A3 © 2009 Microchip Technology Inc. PIC12F508/509/16F505 EXPOSED PAD BOTTOM VIEW A NOTE NOTE DS41236E-page 97 ...
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... PIC12F508/509/16F505 N NOTE DS41236E-page © 2009 Microchip Technology Inc. ...
Page 99
... N NOTE © 2009 Microchip Technology Inc. PIC12F508/509/16F505 φ α c β DS41236E-page 99 ...
Page 100
... PIC12F508/509/16F505 D N NOTE DS41236E-page 100 © 2009 Microchip Technology Inc. φ L ...
Page 101
... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. PIC12F508/509/16F505 DS41236E-page 101 ...
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... PIC12F508/509/16F505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41236E-page 102 © 2009 Microchip Technology Inc. ...
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... Figure 10-2; Section 11.0, Added Char data; Revised Package Marking Information; Revised Product ID System. Revision E (08/2009) Added PIC16F505 16-Pin diagram (QFN); Added Note after subsection 5.2 PORTC; Updated Note 4 and deleted Note 5, Table 10-1; Deleted Param. No. D061 (Table 10-1) and Param. No. D061A becomes D061; ...
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... PIC12F508/509/16F505 NOTES: DS41236E-page 104 © 2009 Microchip Technology Inc. ...
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... Internet Address................................................................ 107 L Loading of PC ..................................................................... 27 M Memory Organization.......................................................... 17 Data Memory .............................................................. 18 Program Memory (PIC12F508/509)............................ 17 Program Memory (PIC16F505)................................... 18 Microchip Internet Web Site .............................................. 107 MPLAB ASM30 Assembler, Linker, Librarian ..................... 66 MPLAB ICD 2 In-Circuit Debugger ..................................... 67 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ...................................................... 67 © 2009 Microchip Technology Inc. ...
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... PIC12F508/509/16F505 W Wake-up from Sleep ........................................................... 55 Watchdog Timer (WDT) ................................................ 41, 52 Period.......................................................................... 52 Programming Considerations ..................................... 52 WWW Address.................................................................. 107 WWW, On-Line Support........................................................ 6 Z Zero bit ................................................................................ 11 DS41236E-page 106 © 2009 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. PIC12F508/509/16F505 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41236E-page 108 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41236E © 2009 Microchip Technology Inc. ...
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... PIC12F508-I/SN = Industrial Temp., SOIC package c) PIC12F508T-E/P = Extended Temp., PDIP package, Tape and Reel (3, 4) (3, 4) (4) Note 1: (4) (4) 2: (4) ( tape and reel SOIC, TSSOP and QFN packages only tape and reel SOIC and MSOP packages only. PIC12F508/PIC12F509 only. Pb-free. PIC16F505 only. DS41236E-page 109 ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...