PIC16F506-I/ST Microchip Technology, PIC16F506-I/ST Datasheet
PIC16F506-I/ST
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... Microchip Technology Inc. PIC16F610/16HV610 PIC16F616/16HV616 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers Preliminary DS41288C ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... MHz, 2.0V, typical • Watchdog Timer Current μA @ 2.0V, typical Note: Voltage across internal shunt regulator cannot exceed 5V. © 2007 Microchip Technology Inc. Peripheral Features: • Shunt Voltage Regulator (PIC16HV610/616 only volt regulation - shunt range • 11 I/O pins and 1 input only ...
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... Preliminary Timers Voltage Range 8/16-bit 2 1/1 2.0-5.5V 2 1/1 2.0-user defined 2 2/1 2.0-5.5V 2 2/1 2.0-user defined SS Basic ICSPDAT ICSPCLK — MCLR/V PP OSC2/CLKOUT OSC1/CLKIN — — — — — — © 2007 Microchip Technology Inc. ...
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... AN7 C12IN3- RC4 6 — C2OUT RC5 5 — — — 1 — — — 14 — — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 RA0/AN0/C1IN+/ICSPDAT 2 13 RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT 4 10 RC0/AN4/C2IN RC1/AN5/C12IN1 RC2/AN6/C12IN2-/P1D 14- ...
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... Preliminary Basic ICSPDAT ICSPCLK — MCLR/V PP OSC2/CLKOUT OSC1/CLKIN — — — — — — © 2007 Microchip Technology Inc. ...
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... RC4 5 — C2OUT RC5 4 — — — 16 — — — 13 — — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 RA0/AN0/C1IN+/ICSPDAT 12 1 RA1/AN1/C12IN0-/ PIC16F616/ PIC16HV616 RA2/AN2/T0CKI/INT/C1OUT 10 3 RC0/AN4/C2IN1 16- PIN SUMMARY Timers CCP Interrupts Pull-ups — ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41288C-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... Bus Instruction Reg 8 Instruction Decode and Control Timing OSC1/CLKIN Generation OSC2/CLKOUT Internal Oscillator Block T1G T1CKI Timer0 T0CKI © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 INT 13 Data Bus Program Counter RAM 8-Level Stack 64 Bytes File (13-Bit) Registers RAM Addr 9 Addr MUX Indirect 7 ...
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... W Reg Timer Brown-out Reset Shunt Regulator (PIC16HV616 only MCLR DD SS Timer1 Timer2 Comparator Voltage Reference 2 Analog Comparators Fixed Voltage Reference Preliminary 8 PORTA RA0 RA1 RA2 RA3 RA4 RA5 PORTC RC0 RC1 RC2 RC3 RC4 RC5 ECCP © 2007 Microchip Technology Inc. ...
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... RC0/C2IN+ RC1/C12IN1- RC2/C12IN2- RC3/C12IN3- RC4/C2OUT RC5 Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Input Output Type Type RA0 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change C1IN+ AN — Comparator C1 non-inverting input ...
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... CMOS PORTC I/O CCP1 ST CMOS Capture input/Compare output P1A — CMOS PWM output V Power — Positive supply DD V Power — Ground reference SS CMOS = CMOS compatible input or output = TTL compatible input Preliminary Description HV = High Voltage XTAL = Crystal © 2007 Microchip Technology Inc. ...
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... PIC16F610/16HV610 PC<12:0> CALL, RETURN 13 RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 2-2: CALL, RETURN RETFIE, RETLW 0000h 0004h 0005h 03FFh 0400h 1FFFh Preliminary PROGRAM MEMORY MAP ...
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... The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. Preliminary and 128 the © 2007 Microchip Technology Inc. ...
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... General Purpose Registers 64 Bytes Accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 2-4: File Address (1) Indirect Addr. 80h TMR0 81h 82h PCL STATUS 83h ...
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... VR1 VR0 0000 0000 70, 113 C1CH1 C1CH0 0000 -000 60, 113 C2CH1 C2CH0 0000 -000 61, 113 T1GSS C2SYNC 00-0 0010 63, 113 — — xxxx xxxx 78, 113 GO/DONE ADON 0000 0000 76, 113 © 2007 Microchip Technology Inc. ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE ...
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... Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R-1 R-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. used by the and R/W-x R/W bit Bit is unknown ...
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... Microchip Technology Inc. PIC16F610/616/16HV610/616 Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”. ...
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... R/W-0 R/W-0 R/W-0 INTE RAIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary should ensure the R/W-0 R/W-0 INTF RAIF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...
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... R/W-0 R/W-0 (1) C2IF C1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) Preliminary U-0 R/W-0 R/W-0 (1) — TMR2IF TMR1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 U-0 U-0 U-0 — — ...
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... Example 2-1. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE Preliminary INDIRECT ADDRESSING 0x40 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR, F ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue © 2007 Microchip Technology Inc. ...
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... For memory map detail, see Figure 2-4. Unimplemented data memory locations, read as ‘0’. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in Bank 2 and Bank 3 are mirrored back into Bank 0 and Bank 1, respectively. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 0 IRP ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 24 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator OSC2 Sleep OSC1 Internal Oscillator INTOSC 8 MHz © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode. 3. ...
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... These oscillator delays are shown in Table 3-1. ® MCU (1) Frequency 4 MHz to 8 MHz DC – 20 MHz 32 kHz to 20 MHz Preliminary Oscillator Delay Oscillator Warm-Up Delay (T ) WARM 2 Instruction Cycles 1024 Clock Cycles (OST) © 2007 Microchip Technology Inc. ...
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... The value of R varies with the Oscillator mode F selected (typically between 2 MΩ MΩ). © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application ...
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... The CLKOUT Clock signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. ) values EXT Preliminary See Section 12.0 “Special © 2007 Microchip Technology Inc. ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 12-1) for operation of all register bits. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 30 Preliminary © 2007 Microchip Technology Inc. ...
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... Note 1: TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. ...
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... PORTA operation is being executed, then the RAIF interrupt flag may not get set. R/W-1 R/W-1 R/W-1 ANS4 ANS3 ANS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) . Preliminary R/W-1 R/W-1 ANS1 ANS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IOCA<5:0>: Interrupt-on-change PORTA Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-1 U-0 R/W-1 WPUA4 — ...
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... ADC • In-Circuit Serial Programming clock Note 1: PIC16F616/16HV616 only. Analog Input Mode (1) Analog Input Mode PORTA To Comparator (3) To A/D Converter Preliminary (1) (1) /C12IN0-/V / REF (1) (1) ( Weak RAPU V DD I/O Pin © 2007 Microchip Technology Inc. ...
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... IOAC RD IOAC ( Interrupt-on- From other Change R RA<5:3, 1:0> pins Write ‘0’ to RAIF Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Analog Input Mode C1OE Enable C1OE ...
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... BLOCK DIAGRAM OF RA3 Data Bus RD TRISA RD PORTA WR IOCA RD IOCA ( Interrupt-on- From other Change R RA<5:4, 2:0> pins Write ‘0’ to RAIF Note 1: Set has priority over Reset DS41288C-page 36 MCLRE Reset PORTA Preliminary V DD Weak MCLRE Input Pin MCLRE © 2007 Microchip Technology Inc. ...
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... Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 • a Timer1 gate (count enable) • a crystal/resonator connection • a clock output Note 1: PIC16F616/16HV616 only ...
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... INTOSC Mode Data Bus WPUA RAPU RD WPUA Oscillator Circuit OSC2 PORTA TRISA INTOSC RD Mode TRISA RD PORTA IOCA RD IOCA From other RA<4:0> pins RD PORTA To Timer1 Preliminary (1) TMR1LPEN V DD Weak V DD I/O Pin © 2007 Microchip Technology Inc. ...
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... RA5 TRISA — — TRISA5 WPUA — — WPUA5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 ANS4 ANS3 ANS2 ANS1 — C1POL ...
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... Bit is cleared Preliminary INITIALIZING PORTC ;Bank 0 ;Init PORTC ;Bank 1 ;digital I/O ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs ;Bank 0 R/W-0 R/W-x R/W-x RC2 RC1 RC0 bit Bit is unknown R/W-1 R/W-1 R/W-1 TRISC2 TRISC1 TRISC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... TRISC RD PORTC To Comparators To A/D Converter Note 1: Analog Input mode comes from ANSEL or Comparator mode. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 4.3.3 RC2/AN6 The RC2 is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • an analog input to Comparators C1 and C2 • ...
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... I/O Pin V SS Value on Value on Bit 0 all other POR, BOR Resets ANS0 1111 1111 1111 1111 CCP1M0 0000 0000 0000 0000 C1CH0 0000 -000 0000 -000 C2CH0 0000 -000 0000 -000 RC0 --xx 00xx --uu 00uu TRISC0 --11 1111 --11 1111 © 2007 Microchip Technology Inc. ...
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... Watchdog WDTE Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...
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... Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 15.0 “Electrical Specifications”. Preliminary © 2007 Microchip Technology Inc. ;Clear WDT and ;prescaler ; ;Mask TMR0 select and ...
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... T0CS TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 46 Preliminary © 2007 Microchip Technology Inc. ...
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... ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 6.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair ...
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... Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator C2 output. This configures Timer1 to measure either the active-high or active-low time between events. Preliminary © 2007 Microchip Technology Inc. the Microchip web site ...
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... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event ...
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... TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register Timer1 gate source. DS41288C-page 50 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON T1GINV TMR1GE T1CKPS1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 C2POL — C2R C2CH1 ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 52 Preliminary © 2007 Microchip Technology Inc. ...
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... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
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... Value on Value on Bit 0 all other POR, BOR Resets RAIF 0000 0000 0000 0000 TMR1IE -000 0-00 -000 0-00 TMR1IF -000 0-00 -000 0-00 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 © 2007 Microchip Technology Inc. ...
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... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 8- ...
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... C2SYNC C2POL D Q From Timer1 Clock Preliminary C1POL To Data Bus RD_CM1CON0 Set C1IF PWM Logic CL C1OE (2) C1OUT pin C2POL To Data Bus RD_CM2CON0 Set C2IF other peripherals C2OE 0 MUX 1 (2) C2OUT pin SYNCC2OUT To Timer1 Gate To SR Latch © 2007 Microchip Technology Inc. ...
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... See Section 8.11 “Comparator Voltage Reference” for more information on the internal voltage reference module. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.2.4 COMPARATOR OUTPUT SELECTION The output of the comparator can be monitored by ...
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... Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. Preliminary © 2007 Microchip Technology Inc. reset by software reset by software ...
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... INTCON register is also set, the device will then execute the interrupt service routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their OFF states. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Preliminary DS41288C-page 59 ...
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... Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port TRIS bit = 0. DS41288C-page 60 R/W-0 U-0 C1POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > C1V - < C1V - > C1V - < C1V - IN IN (1) output REF - Preliminary R/W-0 R/W-0 R/W-0 C1R C1CH1 C1CH0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... C2 connects to C12IN2 C2V - pin of C2 connects to C12IN3- IN Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 U-0 C2POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > ...
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... The analog SS 2: Analog levels on any pin defined as a and the DD digital input, may cause the input buffer to consume more current than is specified ≈ 0. LEAKAGE ≈ 0. ±500 nA Vss Preliminary To ADC Input © 2007 Microchip Technology Inc. ...
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... Timer1 gate source is T1G 0 = Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit Output is synchronous to falling edge of Timer1 clock Output is asynchronous © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 The Comparator C2 output can be synchronized with Timer1 by setting the C2SYNC bit of the CM2CON1 register ...
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... V + rises above the upper hysteresis IN threshold (V +). The output of the comparator changes H from a high state to a low state only when the analog voltage falls below the lower hysteresis IN threshold (V -). H + Output – Preliminary © 2007 Microchip Technology Inc. ...
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... TRISA5 TRISC TRISC5 VRCON C1VREN C2VREN VRR Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 ANS4 ANS3 ANS2 ANS1 C1POL C1SP ...
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... The latch configuration enable states are completely independent of the enable states for the comparators. SR0 (1) Latch R Q SR1 pulse width. OSC Preliminary C1OE 0 MUX 1 (3) C1OUT pin C2OE 1 MUX (3) 0 C2OUT pin © 2007 Microchip Technology Inc. ...
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... SRCS<1:0>: SR Latch Clock Prescale bits /16 OSC /32 OSC /64 OSC /128 OSC bit 5-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 R/S-0 R/S-0 C2REN PULSS PULSR S = Bit is set only - U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) U-0 U-0 U-0 — ...
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... OUTPUT RATIOMETRIC TO VDD The comparator voltage reference is V therefore, the The tested absolute accuracy of the Comparator DD Voltage Reference can be found in Section 15.0 “Electrical Specifications”. DD × /32) DD Preliminary SS derived and DD output changes with fluctuations in REF © 2007 Microchip Technology Inc. ...
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... REF To Comparators and ADC Module C1VREN C2VREN To ADC Module Fixed Ref To Comparators and ADC Module © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.11.7 VOLTAGE REFERENCE SELECTION , with DD Multiplexers on the output of the voltage reference module enable selection of either the CV voltage reference for use by the comparators. ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared input of Comparator C1 REF input of Comparator C1 REF input of Comparator C2 REF input of Comparator C2 REF Value Selection bits (0 ≤ VR<3:0> ≤ 15) REF = (VR<3:0>/24 (VR<3:0>/32 Preliminary R/W-0 R/W-0 VR2 VR1 VR0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Figure 9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM RA0/AN0 RA1/AN1/V REF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 CV REF 0.6V Reference 1.2V Reference CHS <3:0> © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 (ADC) allows V DD VCFG = 0 V VCFG = 1 REF ADC GO/DONE ADFM ADON ...
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... DD ) OSC 4 MHz 1 MHz (2) 2.0 μs 500 ns (2) 1.0 μs 4.0 μs 2.0 μs 8.0 μs (3) 4.0 μs 16.0 μs (3) 8.0 μs (3) 32.0 μs (3) 16.0 μs (3) 64.0 μs (3) 2-6 μs (1,4) 2-6 μs (1,4) © 2007 Microchip Technology Inc. ...
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... Please see Section 9.1.5 “Interrupts” for more information. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 CYCLES ...
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... Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt may be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 9.3 Requirements”. Preliminary © 2007 Microchip Technology Inc. (1) (2) . “A/D Acquisition ...
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... BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Preliminary DS41288C-page 75 ...
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... If the Comparator module uses this VP6 reference voltage, the comparator output may momentarily change state due to the transient. DS41288C-page 76 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... RC 100 = F /4 OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-x R-x ADRES3 ADRES2 bit Bit is unknown U-0 U-0 — — bit Bit is unknown R-x R-x ADRES9 ADRES8 bit Bit is unknown R-x R-x ADRES1 ADRES0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... S Note 1: The reference voltage (V REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 ) SS ) impedance SS = 50°C and external impedance of 10k ...
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... REF DS41288C-page Sampling Switch V = 0.6V T ≤ Rss LEAKAGE V = 0.6V T ± 500 Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale REF Transition Preliminary HOLD REF Sampling Switch (kΩ) © 2007 Microchip Technology Inc. ...
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... TRISA5 TRISC — — TRISC5 Legend unknown unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE ADCS0 — ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 82 Preliminary © 2007 Microchip Technology Inc. ...
Page 85
... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle ...
Page 86
... NEW_CAPT_PS ;Load the W reg with CCPR1L MOVWF CCP1CON TMR1L Preliminary of the CCP1CON register. CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value © 2007 Microchip Technology Inc. ...
Page 87
... TRISA5 TRISC — — TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 ...
Page 88
... CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. Preliminary the match condition by © 2007 Microchip Technology Inc. ...
Page 89
... TRISA5 TRISC — — TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 ...
Page 90
... DS41288C-page 88 The PWM output (Figure 10-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 10-4: Period Pulse Width TMR2 = 0 CCP1 TRIS ), or OSC Preliminary CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4> © 2007 Microchip Technology Inc. ...
Page 91
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 EQUATION 10-2: Pulse Width EQUATION 10-3: • OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle ...
Page 92
... Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output by clearing the associated TRIS bit. Preliminary © 2007 Microchip Technology Inc. ...
Page 93
... Full-Bridge, Forward 01 Full-Bridge, Reverse 11 © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. ...
Page 94
... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.6 “Programmable Dead-Band Delay mode”). DS41288C-page 92 Pulse 0 Width Period (1) (1) Delay Delay Preliminary © 2007 Microchip Technology Inc. PR2+1 ...
Page 95
... OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.6 “Programmable Dead-Band Delay mode”). © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Pulse 0 Width Period (1) (1) Delay Delay ...
Page 96
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver Preliminary EXAMPLE OF HALF- BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2007 Microchip Technology Inc. ...
Page 97
... P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 10-10: EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 V+ QA FET Driver Load FET Driver QB ...
Page 98
... EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41288C-page 96 Period (1) Period (1) Preliminary © 2007 Microchip Technology Inc. ...
Page 99
... When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer2 counts. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 The Full-Bridge mode does not provide dead-band delay ...
Page 100
... Potential Shoot-Through Current Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. OFF DS41288C-page 98 Forward Period Reverse Period Preliminary DC OFF – T OFF ON © 2007 Microchip Technology Inc. ...
Page 101
... Output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Preliminary DS41288C-page 99 ...
Page 102
... Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 103
... FIGURE 10-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM ...
Page 104
... P1B ( Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high OSC V+ FET Driver P1A Load FET Driver P1B V- Preliminary EXAMPLE OF HALF- BRIDGE PWM OUTPUT Period Period td (1) ( © 2007 Microchip Technology Inc. ...
Page 105
... TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 106
... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 104 Preliminary © 2007 Microchip Technology Inc. ...
Page 107
... See Figure 11-1 for voltage regulator schematic. FIGURE 11-1: VOLTAGE REGULATOR V UNREG R I SER SUPPLY I SHUNT C Feedback BYPASS © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 An external current limiting resistor, R between the unregulated supply, V pin, drops the difference in voltage between V pin. DD and SER defined by Equation 11-1. pin DD ...
Page 108
... Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration 3FFFh), which can be accessed only during programming. See “PIC12F60X/12F61X/ 16F61X Memory Programming Specifica- tion” (DS41284) for more information. Preliminary memory space (2000h- © 2007 Microchip Technology Inc. ...
Page 109
... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire program memory will be erased when the code protection is turned off. 3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 — — (3) PWRTE ...
Page 110
... A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 15.0 “Electrical Specifications” for pulse-width specifications. Preliminary S Chip_Reset R Q Enable PWRT Enable OST © 2007 Microchip Technology Inc. ...
Page 111
... MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull- © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 12- This ...
Page 112
... Brown-out Reset and the Power-up Timer will be re-initialized. Once V DD falls rises above V DD BOR . 64 ms Reset. ( & Preliminary rises DD while the Power-up Timer is BOR DD , the Power-up Timer will execute a V BOR V BOR V BOR © 2007 Microchip Technology Inc. ...
Page 113
... Legend unchanged unknown, – = unimplemented bit, reads as ‘0’ value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.3.6 POWER CONTROL (PCON) ...
Page 114
... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS41288C-page 112 T PWRT T OST T PWRT T OST DD T PWRT T OST Preliminary © 2007 Microchip Technology Inc. ) ...
Page 115
... See Table 12-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 MCLR Reset WDT Reset (1) Brown-out Reset uuuu uuuu xxxx xxxx ...
Page 116
... uuu0 0uuu 000h 0001 1uuu ( uuu1 0uuu Preliminary © 2007 Microchip Technology Inc. Interrupt uuuu uuuu 1111 1111 --uu -uuu --uu uuuu uuuu uu-u uu-- ---- uuuu uuuu -uuu ---- PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ...
Page 117
... A/D Interrupt • 2 Comparator Interrupts • Timer1 Overflow Interrupt • Timer2 Match Interrupt • Enhanced CCP Interrupt © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be has multiple three or four instruction cycles ...
Page 118
... Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”. 2: PIC16F616/16HV616 only. Preliminary (1) Wake-up (If in Sleep mode) Interrupt to CPU © 2007 Microchip Technology Inc. ...
Page 119
... ADIF CCP1IF (1) (1) PIE1 — ADIE CCP1IE Legend unknown unchanged, – = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC16F616/16HV616 only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 (1) (2) Interrupt Latency Inst ( — ...
Page 120
... STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS41288C-page 118 and Preliminary © 2007 Microchip Technology Inc. ...
Page 121
... TABLE 12-7: WDT STATUS Conditions WDTE = 0 CLRWDT Command Exit Sleep + System Clock = EXTRC, INTRC, EC Exit Sleep + System Clock = XT, HS, LP © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.6.1 WDT PERIOD The WDT has a nominal time-out period (with no prescaler). The time-out periods vary with temperature part (see Table 15-4, Parameter 31) ...
Page 122
... See Register 12-1 for operation of all Configuration Word register bits. DS41288C-page 120 Bit 4 Bit 3 Bit 2 Bit 1 T0SE PSA PS2 PS1 PWRTE WDTE FOSC2 FOSC1 Preliminary Value on Value on Bit 0 all other POR, BOR Resets PS0 1111 1111 1111 1111 FOSC0 — — © 2007 Microchip Technology Inc. ...
Page 123
... External Interrupt from INT pin. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 When the SLEEP instruction is being executed, the next instruction ( prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 124
... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. DS41288C-page 122 OST (2) T (3) Interrupt Latency Processor in Sleep Inst( Dummy Cycle Inst( not been Specification” Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) © 2007 Microchip Technology Inc. ...
Page 125
... Bulk Erase V minimum given in the DD “PIC12F615/12HV615/16F616/16HV616 Memory Programming (DS41284) © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.11 In-Circuit Debugger Since in-circuit debugging requires access to three pins, MPLAB device is not practical. A special 28-pin PIC16F610/ 616/16HV610/616 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user ...
Page 126
... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 124 Preliminary © 2007 Microchip Technology Inc. ...
Page 127
... PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 TABLE 13-1: OPCODE FIELD DESCRIPTIONS ...
Page 128
... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2007 Microchip Technology Inc. ...
Page 129
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 BCF Syntax: k Operands: Operation: Status Affected: ...
Page 130
... Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Preliminary © 2007 Microchip Technology Inc. f,d ...
Page 131
... Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 INCFSZ Syntax: Operands: Operation: Status Affected: Description: ...
Page 132
... Move label ] MOVWF f 0 ≤ f ≤ 127 (W) → (f) None Move data from W register to register ‘f’ MOVW OPTION F Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP © 2007 Microchip Technology Inc. ...
Page 133
... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 RETLW Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: TABLE DONE RETURN Syntax: Operands: ...
Page 134
... Subtract W from literal [ label ] SUBLW k 0 ≤ k ≤ 255 k - (W) → (W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. Result Condition W > ≤ W<3:0> > k<3:0> W<3:0> ≤ k<3:0> © 2007 Microchip Technology Inc. ...
Page 135
... Operation: Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 XORWF Syntax: Operands: Operation: Status Affected: Description: Preliminary Exclusive OR W with f ...
Page 136
... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 134 Preliminary © 2007 Microchip Technology Inc. ...
Page 137
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 138
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
Page 139
... Microchip Technology Inc. PIC16F610/616/16HV610/616 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 140
... Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. Preliminary © 2007 Microchip Technology Inc. ® L security ICs, CAN ® ...
Page 141
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 ........................................................................... -0. )...............................................................................................................± ...
Page 142
... FIGURE 15-2: PIC16HV610/616 VOLTAGE-FREQUENCY GRAPH, ≤ ≤ -40°C T +125°C A 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41288C-page 140 8 10 Frequency (MHz Frequency (MHz) Preliminary 20 20 © 2007 Microchip Technology Inc. ...
Page 143
... A 125 2.0 2.5 FIGURE 15-4: PIC16HV610/616 VOLTAGE-FREQUENCY GRAPH, ≤ ≤ -40°C T +125°C A 125 2.0 2.5 © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 ± 5% ± 2% ± 1% 3.0 3.5 4.0 4.5 V (V) DD ± 5% ± 2% ± 1% 3.0 3.5 4.0 V (V) DD Preliminary 5.0 5.5 4 ...
Page 144
... V/ms See Section 12.3.1 “Power-on Reset (POR)” for details. can be lowered in Sleep mode without losing RAM data. Preliminary ≤ +85°C for industrial A ≤ +125°C for extended A Conditions < MHz < MHz < MHz < MHz < MHz < MHz < MHz < MHz © 2007 Microchip Technology Inc. ...
Page 145
... For RC oscillator configurations, current through R be extended by the formula I © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 -40°C ≤ T ≤ +85°C for industrial A -40°C ≤ T ≤ ...
Page 146
... REF T1OSC disabled -40°C ≤ T ≤ +25°C A NOTE 3 (1) WDT Current (1) BOR Current (1) Comparator Current , both comparators enabled (1) CV Current (high range) REF (1) CV Current (low range) REF (1) T1OSC Current , 32.768 kHz (1) A/D Current , no conversion in progress © 2007 Microchip Technology Inc. ...
Page 147
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied Shunt regulator is always enabled and always draws operating current. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 -E (Extended) -40°C ≤ T ≤ ...
Page 148
... V DD 2.0V ≤ V ≤ 4. 2.0V ≤ V ≤ 5. (Note 1) μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD μA ≤ V ≤ XT, HS and SS PIN DD LP oscillator configuration μ 5.0V PIN 8.5 mA 4.5V (Ind -3.0 mA 4.5V (Ind © 2007 Microchip Technology Inc. ...
Page 149
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 PIC16F610/616/16HV610/616-I (Industrial) PIC16F610/616/16HV610/616-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) -40° ...
Page 150
... PDIP package 31.0 C/W 14-pin SOIC package 31.7 C/W 14-pin TSSOP package 2.6 C/W 16-pin QFN 4x4mm package 150 C — INTERNAL — INTERNAL (NOTE 1) = Σ (I — — DER MAX (NOTE 2) Preliminary © 2007 Microchip Technology Inc. Conditions + Σ )/θ DIE A JA ...
Page 151
... I/O Port mc MCLR Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 15-5: LOAD CONDITIONS Load Condition Pin Legend for all pins for OSC2 output © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise ...
Page 152
... LP Oscillator mode ns XT Oscillator mode ns HS Oscillator mode ns EC Oscillator mode μs LP Oscillator mode ns XT Oscillator mode ns HS Oscillator mode ns RC Oscillator mode 4/F CY OSC μs LP oscillator ns XT oscillator ns HS oscillator ns LP oscillator ns XT oscillator ns HS oscillator © 2007 Microchip Technology Inc. ...
Page 153
... When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices ensure these oscillator frequency tolerances, V possible. 0.1 μF and 0.01 μF values in parallel are recommended design. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Freq. Min Typ† Max Tolerance — ...
Page 154
... OSC — — ↑ (Q2 cycle) 20 — OSC (2) — 15 — 40 (2) — 28 — — T — CY OSC Preliminary Execute Q3 OS12 OS18 New Value Max Units Conditions 5. 5. — 5.0V DD — 5.0V DD — 5.0V DD — ns — © 2007 Microchip Technology Inc. ...
Page 155
... Note 1: Asserted low. FIGURE 15-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 BOR 37 33* Preliminary 31 34 HYST (Device not in Brown-out Reset) ...
Page 156
... All specified values and V must be capacitively decoupled as close to the device Preliminary Conditions μ 5V, -40°C to +85°C DD μ 5V, +85°C to +125° 5V, -40°C to +85° 5V, +85°C to +125° (NOTE 3) OSC ms μs V (NOTE 4) mV μs ≤ BOR © 2007 Microchip Technology Inc. ...
Page 157
... Delay from External Clock Edge to Timer TMR Increment * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Min Typ† ...
Page 158
... DS41288C-page 156 CC01 CC02 CC03 ≤ +125°C Min No Prescaler 0. With Prescaler 20 No Prescaler 0. With Prescaler Preliminary Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — prescale value ( 16) © 2007 Microchip Technology Inc. ...
Page 159
... VP6 VP6 voltage output OUT VR02 V1P2 V1P2 voltage output OUT VR03 T Settling Time STABLE * These parameters are characterized but not tested. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 ≤ +125°C Min Typ† ± 5.0 — 0 — +55 — Falling — ...
Page 160
... final value μF Bypass capacitor pin μA Includes band gap reference current Conditions = 5.12V REF V = 5.12V REF = 5.12V REF = 5.12V REF Absolute minimum to ensure 1 LSb accuracy During V acquisition. AIN Based on differential HOLD AIN During A/D conversion cycle. © 2007 Microchip Technology Inc. ...
Page 161
... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following T 2: See Section 9.3 “A/D Acquisition Requirements” for minimum conditions. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 ≤ +125°C Min Typ† Max Units μ ...
Page 162
... SLEEP instruction to be executed. DS41288C-page 160 ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the CY ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the CY Preliminary NEW_DATA DONE NEW_DATA DONE © 2007 Microchip Technology Inc. ...
Page 163
... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Preliminary DS41288C-page 161 ...
Page 164
... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 162 Preliminary © 2007 Microchip Technology Inc. ...
Page 165
... Microchip part number, year code, week code, and traceability ® code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 Example PIC16F616 -I/P ...
Page 166
... A1 .015 – E .290 .310 E1 .240 .250 D .348 .365 L .115 .130 c .008 .010 b1 .040 .060 b .014 .018 eB – – Microchip Technology Drawing C04-018B Preliminary c MAX .210 .195 – .325 .280 .400 .150 .015 .070 .022 .430 © 2007 Microchip Technology Inc. ...
Page 167
... Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 D E ...
Page 168
... A1 0.05 – E 6.40 BSC E1 4.30 4.40 D 4.90 5.00 L 0.45 0.60 L1 1.00 REF φ 0° – c 0.09 – b 0.19 – Microchip Technology Drawing C04-087B Preliminary φ L MAX 1.20 1.05 0.15 4.50 5.10 0.75 8° 0.20 0.30 © 2007 Microchip Technology Inc. ...
Page 169
... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 EXPOSED PAD E2 ...
Page 170
... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 168 Preliminary © 2007 Microchip Technology Inc. ...
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... These differences may cause this device to perform differently in your application than the earlier version of this device. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 APPENDIX B: This discusses some of the issues in migrating from ® other PIC devices ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288C-page 170 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC16F610/16HV610.................................................... 7 PIC16F616/16HV616.................................................... 8 PWM (Enhanced)........................................................ 91 RA0 and RA1 Pins ...................................................... 34 RA2 Pins ..................................................................... 35 RA3 Pin....................................................................... 36 RA4 Pin....................................................................... 37 RA5 Pin....................................................................... 38 RC0 and RC1 Pins...................................................... 41 © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 RC2 and RC3 Pins ..................................................... 41 RC4 Pin ...................................................................... 42 RC5 Pin ...................................................................... 42 Resonator Operation .................................................. 27 Timer1 ........................................................................ 47 Timer2 ........................................................................ 53 TMR0/WDT Prescaler ................................................ 43 Watchdog Timer ....................................................... 119 Brown-out Reset (BOR) ...
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... Summary Table ........................................................ 126 INTCON Register................................................................ 18 Internal Oscillator Block INTOSC Specifications ........................................... 151, 152 Internal Sampling Switch (R SS Internet Address ............................................................... 175 Interrupts........................................................................... 115 ADC ............................................................................ 74 Associated Registers ................................................ 117 Context Saving ......................................................... 118 Interrupt-on-Change ................................................... 32 PORTA Interrupt-on-Change .................................... 116 RA2/INT .................................................................... 115 Timer0 ...................................................................... 116 Preliminary © 2007 Microchip Technology Inc. ) Impedance........................ 79 ...
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... PIE1 Register ...................................................................... 19 Pin Diagram PDIP, SOIC, TSSOP................................................. 2, 3 QFN .......................................................................... 4, 5 Pinout Descriptions PIC16F610/16HV610.................................................... 9 PIC16F616/16HV616.................................................. 10 PIR1 Register...................................................................... 20 PORTA................................................................................ 31 Additional Pin Functions ............................................. 32 © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 ANSEL Register ................................................. 32 Interrupt-on-Change ........................................... 32 Weak Pull-Ups.................................................... 32 Associated registers ................................................... 39 Pin Descriptions and Diagrams .................................. 34 RA0............................................................................. 34 RA1............................................................................. 34 RA2............................................................................. 35 RA3............................................................................. 36 RA4 ...
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... Voltage Reference. See Comparator Voltage Reference (CV ) REF Voltage References Associated registers ................................................... 65 VP6 Stabilization ........................................................ ADC Reference Voltage REF EE W Wake-up Using Interrupts ................................................. 121 Watchdog Timer (WDT).................................................... 119 Associated registers ................................................. 120 Specifications ........................................................... 154 WPUA Register................................................................... 33 WWW Address ................................................................. 175 WWW, On-Line Support ....................................................... 6 Preliminary © 2007 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41288C-page 176 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41288C Preliminary © 2007 Microchip Technology Inc. ...
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... Plastic DIP SL = 14-lead Small Outline (3.90 mm Thin Shrink Small Outline (4.4 mm) Pattern: QTP, SQTP or ROM Code; Special Requirements (blank otherwise) © 2007 Microchip Technology Inc. PIC16F610/616/16HV610/616 XXX Examples: Pattern a) PIC16F610/616/16HV610/616-E/P Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC16F610/616/16HV610/616-I/SL = Industrial Temp., SOIC package, 20 MHz ...
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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...