PIC12F615-I/MF Microchip Technology, PIC12F615-I/MF Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12F615-I/MF
Manufacturer Part Number
PIC12F615-I/MF
Description
IC PIC MCU FLASH 1KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(26 pages)
3.PIC12F609T-ISN.pdf
(8 pages)
4.PIC12F615-EMF.pdf
(196 pages)
Specifications of PIC12F615-I/MF
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
8-DFN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
5
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
- PIC12F609T-ISN PDF datasheet #2
- PIC12F609T-ISN PDF datasheet #3
- PIC12F615-EMF PDF datasheet #4
- Current page: 16 of 196
- Download datasheet (3Mb)
PIC12F609/615/12HV609/615
TABLE 2-4:
DS41302B-page 14
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Addr
1:
2:
3:
4:
5:
6:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCTUNE
PR2
APFCON
WPU
IOC
ADRESL
ANSEL
Name
(2)
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
TRISIO3 always reads as ‘1’ since it is an input only pin.
Read only register.
PIC12F615/HV615 only.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(5, 6)
PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Module Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
GPPU
IRP
Bit 7
GIE
—
—
—
—
—
—
—
—
—
(1)
INTEDG
ADCS2
RP1
PEIE
ADIE
Bit 6
—
—
—
—
—
—
—
(1)
TRISIO5
CCP1IE
ADCS1
WPU5
T0CS
Bit 5
IOC5
T0IE
RP0
—
—
—
—
TRISIO4
T1GSEL
ADCS0
WPU4
TUN4
T0SE
Bit 4
INTE
IOC4
TO
—
—
Write Buffer for upper 5 bits of Program Counter
TRISIO3
TUN3
ANS3
CMIE
GPIE
IOC3
Bit 3
PSA
PD
—
—
—
(4)
TRISIO2
WPU2
TUN2
ANS2
IOC2
Bit 2
T0IF
PS2
—
—
—
Z
TRISIO1
P1BSEL
TMR2IE
WPU1
TUN1
ANS1
INTF
IOC1
Bit 1
POR
PS1
DC
© 2008 Microchip Technology Inc.
TRISIO0
TMR1IE
P1ASEL
GPIF
WPU0
TUN0
ANS0
IOC0
Bit 0
BOR
PS0
C
(3)
xxxx xxxx 22, 103
1111 1111 16, 103
0000 0000 22, 103
0001 1xxx 15, 103
xxxx xxxx 22, 103
--11 1111 31, 103
---0 0000 22, 103
0000 0000 17, 103
-00- 0-00 18, 103
---- --qq 20, 103
---0 0000 29, 103
1111 1111 52, 103
---0 --00 18, 103
--11 -111 34, 103
--00 0000 34, 103
xxxx xxxx 73, 103
-000 1111 33, 103
POR, BOR
Value on
—
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—
—
—
—
—
—
—
—
—
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—
Page
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