PIC16F610-I/ML Microchip Technology, PIC16F610-I/ML Datasheet - Page 20
![IC PIC MCU FLASH 1KX14 16QFN](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F610-I/ML
Manufacturer Part Number
PIC16F610-I/ML
Description
IC PIC MCU FLASH 1KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC12F609T-ISN.pdf
(26 pages)
2.PIC16F616T-ISL.pdf
(214 pages)
3.PIC16F616T-ISL.pdf
(8 pages)
Specifications of PIC16F610-I/ML
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
11
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Controller Family/series
PIC16F
No. Of I/o's
12
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS-232 , USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
11
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFN
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 20 of 214
- Download datasheet (4Mb)
PIC16F610/616/16HV610/616
2.2.2.3
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, PORTA change and
external RA2/INT pin interrupts.
REGISTER 2-3:
DS41288F-page 20
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
GIE
2:
IOCA register must also be enabled.
T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
INTCON Register
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
RAIE: PORTA Change Interrupt Enable bit
1 = Enables the PORTA change interrupt
0 = Disables the PORTA change interrupt
T0IF: Timer0 Overflow Interrupt Flag bit
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
RAIF: PORTA Change Interrupt Flag bit
1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software)
0 = None of the PORTA <5:0> pins have changed state
R/W-0
PEIE
INTCON: INTERRUPT CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
T0IE
R/W-0
INTE
(2)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
RAIE
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
R/W-0
T0IF
software
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
INTF
should
ensure
R/W-0
RAIF
bit 0
the
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