PIC12F635-I/SN Microchip Technology, PIC12F635-I/SN Datasheet - Page 4

• Manufacturer Part Number: PIC12F635-I/SN
• Description: IC MCU FLASH 1KX14 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/SPI/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029, DV164101, DM163014
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162057 - MPLAB ICD 2 HEADER 14DIP
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F635
4.
3. Module: Wake-up Reset (WUR)
DS80203K-page 4
If periodic interrupts are occurring in addition to
the EEIF interrupts, then use a secondary flag to
sense write completion. The secondary flag is
set whenever data EEPROM writes are active. A
data EEPROM write completion is indicated
when the secondary flag is set and the WR flag
is clear.
Affected Silicon Revisions
If a Wake-up Reset occurs when the Wake-up
Reset (WURE) and Power-up Timer (PWTRE)
Configuration bits are enabled, then there will not
be a 72 ms time delay from the Power-up Timer, as
expected.
Work around
None.
Affected Silicon Revisions
A1
A1
X
X
B2
B2
B3
B3
4. Module: Internal/External Clock Switch
If a Wake-up Reset occurs when the Wake-up
Reset (WURE) and Internal/External Clock Switch
Over (IESO) Configuration bits are enabled and
there is no external clock applied to the chip when
in the XT/HS configurations, the processor will
remain in Reset and not begin executing
instructions.
Work around
There is no work around for revision A silicon for
this errata. However, this issue was corrected for
revision B silicon. If a Wake-up Reset occurs when
the Wake-up Reset and Internal/External Clock
Switch Over Configuration bits are enabled in
revision B silicon and Wake-up Reset occurs, the
chip will wake up and reset as expected.
Affected Silicon Revisions
A1
X
B2
Over (IESO)
B3
© 2009 Microchip Technology Inc.