PIC12F635-I/SN Microchip Technology, PIC12F635-I/SN Datasheet - Page 24

• Manufacturer Part Number: PIC12F635-I/SN
• Description: IC MCU FLASH 1KX14 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/SPI/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029, DV164101, DM163014
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162057 - MPLAB ICD 2 HEADER 14DIP
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F635/PIC16F636/639
TABLE 2-2:
DS41232D-page 22
Addr
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
9Bh
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCCON
OSCTUNE
LVDCON
WPUDA
IOCA
WDA
VRCON
EEDAT
EEADR
EECON1
EECON2
2:
3:
Name
(2)
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
GP3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set
again if the mismatch exists.
—
—
—
—
—
—
—
—
—
—
—
(2)
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory
(not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
EEPROM Control Register 2 (not a physical register)
Unimplemented
Unimplemented
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
VREN
RAPU
EEIE
Bit 7
GIE
IRP
—
—
—
—
—
—
—
—
—
—
INTEDG
IRCF2
LVDIE
PEIE
Bit 6
RP1
—
—
—
—
—
—
—
—
—
—
ULPWUE SBOREN
WPUDA5 WPUDA4
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
IRVST
IOCA5
IRCF1
WDA5
T0CS
CRIE
Bit 5
T0IE
VRR
RP0
—
—
—
Write Buffer for upper 5 bits of Program Counter
LVDEN
IOCA4
IRCF0
WDA4
T0SE
TUN4
INTE
Bit 4
TO
—
—
—
WRERR
IOCA3
OSTS
TUN3
RAIE
WUR
Bit 3
C1IE
PSA
VR3
PD
—
—
—
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
OSFIE
IOCA2
WREN
LVDL2
WDA2
TUN2
Bit 2
T0IF
HTS
VR2
PS2
—
Z
IOCA1
LVDL1
WDA1
TUN1
INTF
Bit 1
POR
VR1
PS1
LTS
WR
DC
—
TMR1IE 000- 00-0
RAIF
LVDL0
IOCA0
© 2007 Microchip Technology Inc.
WDA0
TUN0
Bit 0
BOR
SCS
VR0
PS0
RD
C
(3)
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---0 0000
0000 000x
--01 q-qq
-110 q000
---0 0000
--00 -000 --00 -000
--00 0000 --00 0000
--11 -111 --11 -111
0-0- 0000 0-0- 0000
---- x000 ---- q000
---- ---- ---- ----
POR/BOR/
Value on
WUR
—
—
—
—
—
—
—
—
—
—
—
32,137
63,137
32,137
26,137
32,137
32,137
28,137
29,137
31,137
36,137
40,137
Page
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