PIC12F635-I/MD Microchip Technology, PIC12F635-I/MD Datasheet - Page 3

• Manufacturer Part Number: PIC12F635-I/MD
• Description: IC PIC MCU FLASH 1KX14 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-I/MD

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNAC162057 - MPLAB ICD 2 HEADER 14DIPXLT08DFN - SOCKET TRANSITION ICE 8DFN
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: Resets
1.1 Resets (when WDT times out)
1.2 Timer0 and WDT Prescaler Assignment
• Timer0 external clock input (TOCKI) is enabled.
• The Prescaler is assigned to the WDT, then to the
• During the assignments, the TOCKI pin is high
• The 1:1 Prescaler option is chosen.
© 2009 Microchip Technology Inc.
Note:
Timer0 and back to the WDT.
when bit TOSE is set, or low when TOSE is clear.
Modifying the settings of the shared Timer0 and
Watch-dog Timer prescaler may cause device
Resets. If the OPTION_REG bits: PS<2:0> are
changed from any other value to ‘000’, multiple
spurious Resets can occur when the WDT times
out. These Resets can occur even when the PSA
bit is clear, assigning the prescaler to the Timer0.
Work around
If a CLRWDT instruction is issued before the WDT
times out and before the OPTION register
PS<2:0> bits are modified, this problem is
eliminated.
Affected Silicon Revisions
Spurious Reset
A Spurious Reset may occur if the Timer0/Watch-
dog Timer (WDT) prescaler is assigned from the
WDT to Timer0 and then back to the WDT.
Summary
The issue only arises when all of the below
conditions are met:
Description
On a POR, the Timer0/WDT prescaler is assigned
to the WDT. If the prescaler is reassigned to
Timer0 and Timer0 external clock input (TOCKI) is
enabled, then the prescaler would be clocked by a
transition on the TOCKI pin. On power-up, the
TOCKI pin is (by default) enabled for Timer0 in the
OPTION register.
A1
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B3).
B2
B3
• High and Timer0 is configured to transition on a
• Low and Timer0 is configured to transition on a
1.
2.
3.
2. Module: Data EEPROM Memory
1.
2.
3.
falling edge (TOSE set), or
rising edge (TOSE clear)
If the TOCKI pin is:
Then, if the prescaler is reassigned to the WDT, a
clock pulse to the prescaler will be generated on
the reassignment.
If the prescaler is configured for the 1:1 option, the
clock pulse will incorrectly cause a WDT Time-out
Reset of the device.
Work around
Disable the Timer0 external clock input by
clearing the TOCKI bit in the OPTION register.
Modify the TOSE bit in the OPTION register to
the opposite configuration for the logic level on
the TOCKI pin.
Select a prescaler rate, other than 1:1, and issue
a CLRWDT instruction before switching to the
final prescaler rate.
Affected Silicon Revisions
The EEIF flag may be cleared inadvertently when
performing operations on the PIR1 register,
simultaneously with the completion of a data
EEPROM write. This condition occurs when the
data EEPROM write timer completes at the same
moment that the PIR1 register operation is
executed. Register operations are those that have
the PIR1 register as the destination and include,
but are not limited to, BSF, BCF, ANDWF, IORWF
and XORWF.
Work around
Avoid operations on the PIR1 register when
writing to the data EEPROM memory.
Poll the WR bit (EECON1<1>) to determine
when the write is complete.
Use a timer interrupt to catch any instances
when the EEIF flag is inadvertently cleared. The
timer interrupt should be set longer than 8 ms. If
EEIF fails, then the timer interrupt occurs as a
default time out. The WR and WRERR flags are
checked as part of the timer Interrupt Service
Routine to verify the data EEPROM write
success.
A1
X
B2
X
B3
X
PIC12F635
DS80203K-page 3