PIC16F688-I/SL Microchip Technology, PIC16F688-I/SL Datasheet - Page 30

• Manufacturer Part Number: PIC16F688-I/SL
• Description: IC PIC MCU FLASH 4KX14 14SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/SL

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SO-1 - SOCKET TRANSITION 14SOIC 150/208AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
FIGURE 3-7:
3.7
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 3-8:
The FSCM function is enabled by setting the FCMEN
bit in the Configuration Word (CONFIG). It is applicable
to all external clock options (LP, XT, HS, EC, RC or IO
modes).
In the event of an external clock failure, the FSCM will
set the OSFIF bit (PIR1<2>) and generate an oscillator
fail interrupt if the OSFIE bit (PIE1<2>) is set. The
device will then switch the system clock to the internal
oscillator. The system clock will continue to come from
the internal oscillator unless the external clock recovers
and the Fail-Safe condition is exited.
DS41203B-page 28
Program Counter
LFINTOSC
Oscillator
System Clock
Fail-Safe Clock Monitor
Primary
Clock
INTOSC
OSC1
OSC2
÷ 64
Q1
TWO-SPEED START-UP
FSCM BLOCK DIAGRAM
0
Detector
Q2
Clock
Fail
1
T
T
OST
Q3
1022 1023
PC
Clock
Failure
Detected
Q4
Preliminary
Q1
Q2
The frequency of the internal oscillator will depend
upon
(OSCCON<6:4>).
condition, the OSTS bit (OSCCON<3>) is automati-
cally cleared to reflect that the internal oscillator is
active and the WDT is cleared. The SCS bit
(OSCCON<0>) is not updated. Enabling FSCM does
not affect the LTS bit.
The FSCM sample clock is generated by dividing the
INTRC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 3-8 shows the FSCM block diagram.
On the rising edge of the sample clock, the monitoring
latch (CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In the event that a falling edge of the sample
clock occurs, and the monitoring latch is not set, a clock
failure has been detected. The assigned internal
oscillator is enabled when FSCM is enabled as
reflected by the IRCF.
Note:
Note:
the
PC + 1
Two-Speed
enabled when the Fail-Safe Clock Monitor
mode is enabled.
Primary clocks with a frequency ~488 Hz
will be considered failed by the FSCM. A
slow starting oscillator can cause an
FSCM interrupt.
value
Q3
Upon
contained
 2004 Microchip Technology Inc.
Start-up
Q4
entering
in
is
the
PC + 2
the
automatically
Q1
IRCF
Fail-Safe
bits