ATTINY13V-10MU Atmel, ATTINY13V-10MU Datasheet - Page 7
![IC MCU AVR 1K FLASH 10MHZ 20MLF](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY13V-10MU
Manufacturer Part Number
ATTINY13V-10MU
Description
IC MCU AVR 1K FLASH 10MHZ 20MLF
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY13V-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Package
20MLF EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY13V-10MU
Manufacturer:
Atmel
Quantity:
10
- Current page: 7 of 176
- Download datasheet (3Mb)
4. CPU Core
4.1
2535J–AVR–08/10
Architectural Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 4-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
Control Lines
Instruction
Instruction
Program
Memory
Register
Decoder
Flash
Block Diagram of the AVR Architecture
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
Comparator
I/O Module1
I/O Module 2
I/O Module n
Watchdog
Interrupt
Timer
Analog
Unit
7
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