ATTINY13A-PU Atmel, ATTINY13A-PU Datasheet - Page 86
ATTINY13A-PU
Manufacturer Part Number
ATTINY13A-PU
Description
IC MCU AVR 1K FLASH 20MHZ 8PDIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY13A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
64Byte
# I/os (max)
6
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
8
Package Type
PDIP
Package
8PDIP
Family Name
ATtiny
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
86
ATtiny13A
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure 14-6
this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the
trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 14-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high.
Figure 14-7. ADC Timing Diagram, Free Running Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
below. This assures a fixed delay from the trigger event to the start of conversion. In
MUX and REFS
Update
1
Conversion
Complete
2
One Conversion
11
3
Sample &
Hold
4
12
5
13
6
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
9
2
MUX and REFS
Update
10
Conversion
Complete
3
11
Sample & Hold
12
4
13
Sign and MSB of Result
LSB of Result
8126E–AVR–07/10
Next Conversion
1
Prescaler
Reset
2