ATTINY25-20MU Atmel, ATTINY25-20MU Datasheet - Page 226

• Manufacturer Part Number: ATTINY25-20MU
• Description: IC MCU AVR 2K FLASH 20MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.7
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28.10 Rev. 2586D-02/06
28.11 Rev. 2586C-06/05
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Rev. 2586G-05/06
Rev. 2586F-04/06
Rev. 2586E-03/06
ATtiny25/45/85
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All references to power-save mode are removed.
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“Software BOD Disable” on page
“Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page
“Default Clock Source” on page
“Low-Frequency Crystal Oscillator” on page
“Calibrated Internal Oscillator” on page
“Clock Output Buffer” on page
“Power Management and Sleep Modes” on page
Figure 16-1 on page
“Bit 6 – ACBG: Analog Comparator Bandgap Select” on page
“Register Summary” on page
“Digital Input Enable and Sleep Modes” on page
Table 20-16 on page
“Ordering Information” on page
Table 17-2 on page
Table 17-3 on page
“Errata” on page
“Timer/Counter1 in PWM Mode” on page
“Register Summary” on page
“Ordering Information” on page
“Features” on page
Figure 1-1 on page
“Register Summary” on page
“Ordering Information” on page
Table 6-13 on page
Table 20-16 on page
“Bit 2 – TOV1: Timer/Counter1 Overflow Flag” on page
Table 17-2 on page
“DC Characteristics” on page
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“Analog to Digital Converter” on page
“Analog to Digital Converter” on page
Table 6-5 on page
“Errata ATtiny45” on page
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