PIC16F785-I/SS Microchip Technology, PIC16F785-I/SS Datasheet - Page 61

• Manufacturer Part Number: PIC16F785-I/SS
• Description: IC PIC MCU FLASH 2KX14 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164307 - MODULE SKT FOR PM3 28SSOP
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CCPR1L and DC1B<1:0> can be written to at any time,
but the duty cycle value is not latched into CCPR1H
until after a match between PR2 and TMR2 occurs
(i.e. the period is complete). In PWM mode, CCPR1H
is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Because of the buffering, the module waits until the
timer resets, instead of starting immediately. This
means that enhanced PWM waveforms do not exactly
match the standard PWM waveforms, but are instead
offset by one full instruction cycle (4 T
TABLE 8-3:
8.3.3
In Sleep mode, all clock sources are disabled. Timer2
will not increment, and the state of the module will not
change. If the RC5/CCP1 pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
8.3.3.1
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the CCP to be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See Section 3.0 “Clock Sources” for additional
details.
8.3.4
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
 2004 Microchip Technology Inc.
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
Note 1: Changing duty cycle will cause a glitch.
PWM Frequency
OPERATION IN SLEEP MODE
EFFECTS OF A RESET
OPERATION WITH FAIL-SAFE
CLOCK MONITOR
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F
1.22 kHz
0xFF
16
10
OSC
).
(1)
4.88 kHz
0xFF
Preliminary
10
4
(1)
19.53 kHz
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the RC5/CCP1 pin is cleared.
The maximum PWM resolution is a function of PR2 as
shown by Equation 8-3.
EQUATION 8-3:
8.3.5
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
6.
0xFF
Note:
10
1
Configure the PWM pin (RC5/CCP1) as an input
by setting the TRISC<5> bit.
Set the PWM period by loading the PR2 register.
Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
• Set the TMR2 prescale value by loading the
• Enable Timer2 by setting the TMR2ON bit
Enable PWM output after a new PWM cycle has
started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Enable the RC5/CCP1 pin output by clearing
the TMR2IF bit (PIR1<1>).
T2CKPS bits (T2CON<1:0>).
(T2CON<2>).
the TRISC<5> bit.
Resolution
If the PWM duty cycle value is longer than
the PWM period, the assigned PWM pin(s)
will remain unchanged.
SETUP FOR PWM OPERATION
78.12 kHz
0x3F
1
8
OSC
=
log
----------------------------------------- bits
= 20 MHz)
PIC16F785
4 PR2
log
156.3 kHz
0x1F
2
1
7
+
1
DS41249A-page 59
208.3 kHz
0x17
6.6
1