PIC16F722-I/ML Microchip Technology, PIC16F722-I/ML Datasheet - Page 43

• Manufacturer Part Number: PIC16F722-I/ML
• Description: IC PIC MCU FLASH 2KX14 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F722-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 25
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.0
The PIC16F72X/PIC16LF72X device family features
an interruptible core, allowing certain events to
preempt normal program flow. An Interrupt Service
Routine (ISR) is used to determine the source of the
interrupt and act accordingly. Some interrupts can be
configured to wake the MCU from Sleep mode.
FIGURE 4-1:
© 2009 Microchip Technology Inc.
IOC-RB0
IOC-RB1
IOC-RB2
IOC-RB3
IOC-RB4
IOC-RB5
IOC-RB6
IOC-RB7
IOCB0
IOCB1
IOCB2
IOCB3
IOCB4
IOCB5
IOCB6
IOCB7
INTERRUPTS
INTERRUPT LOGIC
TMR1GIE
TMR1GIF
TMR2IE
TMR1IF
TMR1IE
TMR2IF
CCP1IF
CCP1IE
CCP2IF
CCP2IE
SSPIF
SSPIE
RCIE
RCIF
ADIF
ADIE
TXIF
TXIE
PIC16F72X/PIC16LF72X
The PIC16F72X/PIC16LF72X device family has 12
interrupt sources, differentiated by corresponding
interrupt enable and flag bits:
• Timer0 Overflow Interrupt
• External Edge Detect on INT Pin Interrupt
• PORTB Change Interrupt
• Timer1 Gate Interrupt
• A/D Conversion Complete Interrupt
• AUSART Receive Interrupt
• AUSART Transmit Interrupt
• SSP Event Interrupt
• CCP1 Event Interrupt
• Timer2 Match with PR2 Interrupt
• Timer1 Overflow Interrupt
• CCP2 Event Interrupt
A block diagram of the interrupt logic is shown in
Figure 4-1.
Note 1:
RBIE
INTF
INTE
RBIF
PEIE
T0IF
T0IE
GIE
Some peripherals depend upon the
system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See Section 19.1
“Wake-up from Sleep”.
Wake-up (If in Sleep mode)
Interrupt to CPU
DS41341E-page 43
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